EE6378 Bandgap Voltage Reference Circuit

EE6378 Power Management Circuits
EE6378 Power Management Circuits
Lecture 4: Voltage References
g
I t t P f H i L
Instructor: Prof. Hoi Lee
Mixed-Signal & Power IC Laboratory
Mixed Signal & Power IC Laboratory
Department of Electrical Engineering
The University of Texas at Dallas
Introduction
ƒ Here, we will learn to build a reference voltage to provide a stable
and accurate supply voltage. The voltage reference is an
electronic circuit to provide an accurate and stable DC voltage
that is very insensitive to the change in supply voltage and
that is very insensitive to the change in supply voltage and
temperature
ƒ How accurate is a voltage reference? E.g. Weston cell is an
How accurate is a voltage reference? E.g. Weston cell is an
electrochemical device which provides a reproducible voltage of
1.018636 V at 20oC with a small temperature coefficient of 40
ppm/oC. For integrated circuit implementation, active solid-state
de ices can achie e a tempco of 1 4 ppm/oC if appropriate
devices can achieve a tempco of 1-4 ppm/oC if appropriate
compensation technique is employed
ƒ Note
ƒ Note
• To minimize error due to self-heating, voltage reference usually
operates with modest current (e.g. < 1mA)
• Tempco = temperature coefficient, usually expressed in ppm/oC
EE6378 Lecture 4 © 2009 H. Lee pg. 2
p p , y p pp
(parts per million/oC or 10-6/oC

Overview
ƒ Performance Requirements
ƒ Zener Diode Voltage Reference
ƒ Bandgap Voltage References
ƒ Bandgap Voltage References Implemented in
CMOS technologies
Performance Parameters (1)
The primary requirements of a voltage reference are accuracy and
stability. Some qualitative parameters are:
ƒ Load Regulation = ΔVo/ΔIo (usually expressed in mV/mA or mV/A) or
Load Regulation = 100(ΔVo/ΔIo) (in %/mA or %/A)
ƒ Line Regulation = ΔVo/ΔVin (usually expressed in mV/V) or
Line Regulation = 100(ΔVo/ΔVin) (in %/V)
ƒ Power Supply Rejection Ratio (PSRR) is a measure of the ripple in the
reference voltage due to the ripples in the supply voltage
ro
ri
V
V
PSRR 10
log
20
= (in dB)

Example of line regulation / supply-voltage dependence at VDD = 3.3, 4.15
and 5V (step size of 0.85V)
VDD=5V
VDD=4.15V
VDD=3.3V
V
mV
V
V
V
V
V
V
C
DD
ref
DD
ref /
7
.
14
3
3
5
176
.
1
201
.
1
3
3
5
)
3
.
3
(
)
5
(
is
27
T
at
regulation
Line o
=
−
=
=
−
=
=
3
.
3
5
3
.
3
5 −
−
The maximum (Vref(max)) and minimum (Vref(min)) reference voltages are
1.1761V and 1.1731V, respectively. The reference voltage at T = 27oC
(V ) i 1 1761V Th t i / C b f d b
(Vref) is 1.1761V. The tempco in ppm/oC can be found by
C
ppm
T
T
V
V
V O
ref
ref
ref
/
5
.
25
)
0
100
(
10
1761
.
1
1731
.
1
1761
.
1
)
(
10
Tempco
6
min
max
6
(min)
(max)
=
−
×
−
=
−
×
−
=
T
T
Vref )
0
100
(
1761
.
1
)
( min
max

Overview
CMOS technologies
Review on Zener Diode Voltage Reference
ƒ The Zener diode described in Lecture 2 can be considered as a
voltage reference. Since the breakdown voltage due to Zener
breakdown mechanism has a negative temperature coefficient, and
the breakdown voltage due to the avalanche multiplication has a
positive coefficient, the reference voltage is somewhat independent
of the change of temperature
L
z
s
z
s
ZK
z
s
s
in
z
s
z
o I
r
R
r
R
V
r
R
R
V
r
R
r
V
+
−
+
+
+
=
z
s
z
s
z
s
z
o
r
R
r
ΔV
ΔV
+
=
=
Regulation
Line
z
s
z
s
L
o
z
s
in
r
R
r
R
-
ΔI
ΔV
r
R
ΔV
+
=
=
+
Regulation
Load

Improved Zener Diode Reference (1)
ƒ In the case of Zener diode, the output voltage Vo heavily depends on
the load current IL, which in most cases are not good. It would be
better if we could shield the Vz from the influence of the load. This
z
can be done with the help of an op amp as shown below. This
method refers to self regulation which shifts the burden of line and
load regulations from the diode to the op amp
Improved Zener Diode Reference (2)
B i ti
ƒ By inspection,
.
10
2
.
6
)
39
24
1
(
)
1
(
1
2 V
k
k
V
R
R
V z
o =
+
=
+
=
ƒ The output voltage is also adjustable
via R2
ƒ The load current IL is supplied from the
.
10
2
.
6
)
39
24
1
(
)
1
(
1
2
V
k
k
V
R
R
V z
o =
+
=
+
=
39
1 k
R
L pp
opamp such that the current flowing
through the Zener diode is almost
constant at
ƒ Since the diode current is independent
.
15
.
1
3
.
3
2
.
6
0
.
10
3
mA
k
R
V
V
I z
o
z =
−
=
−
=
p
of the load current, the diode voltage is
insensitive to the load
ƒ R3 can be raised to avoid unnecessary
power wastage and self-heating effects
power wastage and self heating effects

Load Regulation (1)
ƒ The load regulation is directly related to the output
impedance. To find Ro, we suppress the input source
Vz and apply the test-voltage technique. By voltage
divider formula:
divider formula:
v
R
r
R
r
R
v
in
in
N
2
1
1
//
//
+
=
ƒ Summing currents at the output node
0
=
−
−
+
−
+ N
N v
Av
v
v
i
ƒ Eliminating vN and solving for the Ro=v/I, we obtain
0
2
=
+
+
o
r
R
i
1
2
1
2
1
where
)]
/
/
1
/(
)
/
/
[(
1
R
b
r
r
R
R
R
r
r
R
r
A
r
R
o
in
in
o
o
o
o
=
≈
+
+
+
+
+
=
2
1
where
1 R
R
b
Ab +
+
Load Regulation (2)
ƒ Typically rin is in the MΩ range or
greater, R1 and R2 are in kΩ range
and ro is on the order of 102 Ω. The
t /R / d R / th
terms ro/R1, ro/rin, and R2/rin can thus
be ignored to yield Ro≈ro/(1+Ab)
ƒ The load regulation R r /(1+Ab)
ƒ The load regulation Ro≈ro/(1+Ab)
which is much smaller than the Zener
diode voltage reference without
opamp
p p
ƒ Since ro and A are frequency
dependent, so are the load
regulation. In general, load regulation
tends to degrade with frequency

Thermal Stability (1)
ƒ Thermal stability is one of the most demanding performance
requirement of voltage references due to the fact that semiconductor
components are strongly influenced by temperature
ƒ The for ard bias oltage V and c rrent I of a silicon pn j nction
ƒ The forward-bias voltage VD and current ID of a silicon pn junction,
which forms the basis of the diodes and BJTs, are related as
VD=VTln(ID/IS), where VT is the thermal voltage and IS is the saturation
current. Their expressions are
p
where
)
/
exp(
and
/ 0
3
T
G
S
T V
V
BT
I
q
kT
V −
=
=
k=1.381×10-23 is Boltzmann’s constant
q=1.602 ×10-23 C is the electron charge
T is the absolute temperature
p
B is a proportionality constant
VG0 = 1.205V is the bandgap voltage for silicon
Thermal Stability (2)
ƒ The temperature coefficient (TC) of the thermal voltage:
C
mV/
0862
0
)
(
TC o
=
=
∂
=
k
V
V T
T C
mV/
0862
.
0
)
(
TC =
=
∂
=
q
T
VT
)
3
(
)
ln
3
(
]
[ln
)
ln(
)
(
TC 0
0
k
V
V
V
V
T
V
V
I
I
V
I
V
V D
G
T
G
D
S
D
D
T
+
−
=
−
∂
=
∂
+
∂
=
Assume VD=650mV at 25oC, we get TC(VD) ≈ -2.1mV/oC.
)
-(
)
ln(
)
(
TC
q
T
T
V
T
T
V
I
T
V T
T
S
D +
=
∂
−
=
∂
+
∂
=
ƒ TC(VT) have a positive tempco and TC(VD) have a negative tempco,
so these two equations form the basis of two common approaches to
thermal stabilization, namely, thermal compensated Zener diode
, y, p
references and bandgap references

Thermally Compensated Zener Diode Reference
ƒ Idea of thermally compensated Zener diode is to connect a forward-
biased diode in series with a Zener diode having an equal but
opposing tempco as shown below
ƒ Since TC(Vz) is a function of Vz and Iz. We can fine tune Iz to drive
the tempco of the composite device to zero. In this case, a 7.5mA is
p p ,
used to give a reference voltage of Vz = 5.5+0.7 = 6.2V with tempco
ranging from 100ppm/oC to 5ppm/oC
Overview
CMOS technologies

Bandgap Voltage Reference (1)
ƒ Since the best breakdown voltages of the Zener diode references
range from 6 to 7V, they usually require supply voltages on the order
of 10V to operate. This can be a drawback in systems powered from
l li h V Thi li i i i b b d
lower supplies, such as 5V. This limitation is overcome by bandgap
voltage references, so called because their output is determined
primarily by the bandgap voltage of silicon VG0 = 1.205V
Bandgap Voltage Reference (2)
ƒ Addition of the voltage drop V of a base-emitter
ƒ Addition of the voltage drop VBE of a base-emitter
junction, which has a negative tempco, to a voltage
proportional to the thermal voltage VT, which has a
iti t t t f lt hi h
positive tempco, to generate a reference voltage, which
is independent of temperature

Fundamentals
ƒ As TC(VBE) ≈ -2.1mV/°C and TC(VT) = 0.0086mV/°C, then zero tempco is
achieved at a particular temperature (e.g. T=300K):
1
2
)
(
0
)
(
)
(
|
)
(
i.e. 300
−
=
⋅
+
=
+
=
BE
T
BE
K
BG
T
BE
BG
V
TC
V
TC
K
V
TC
V
TC
KV
V
V
ƒ If for a particular transistor with certain bias current such that VBE =
4
.
24
086
.
0
1
.
2
)
(
)
(
=
=
−
=
⇒
T
BE
V
TC
V
TC
K
If for a particular transistor with certain bias current such that VBE =
650mV, then
V.
28
.
1
)
0259
.
0
(
4
.
24
65
.
0 =
+
=
+
= T
BE
BG KV
V
V
ƒ Note that VT = kT/q ∝ T, i.e. VT is proportional to absolute temperature.
We call VT a Proportional To Absolute Temperature voltage, or in short,
PTAT voltage
Bandgap Voltage Reference Circuit (1)
ƒ From the figure, the emitter area of Q1 is n
times as large as the emitter area of Q2,
then Is1/Is2 = n
ƒ By op amp action with identical collector
resistances, the collector currents are also
identical, i.e. IC1 = IC2. Ignore the base
currents we have KV = R (I +I ) = 2R I
)
ln(
)
ln(
1
1
1
2
1
2
3 n
V
I
I
I
I
V
V
V
IR T
S
C
S
C
T
BE
BE =
=
−
=
currents, we have KVT = R4(IC1+IC2) = 2R4I
)
ln(
)
ln(
1
1
1
2
1
2
3 n
V
I
I
I
I
V
V
V
IR T
S
C
S
C
T
BE
BE =
=
−
=
Combine two equations give
T n
R
V
R
K )
ln(
2
2 4
4 =
=
T
BE
T
BE
BG
T
V
n
R
R
V
KV
V
V
n
R
R
V
K
)
ln
2
(
)
ln(
2
3
4
2
2
3
3
+
=
+
=
⇒
=
=

Bandgap Voltage Reference Circuit (2)
F th i di i f
ƒ From the previous discussion, for a zero
tempco voltage reference VBG, K ≈ 24,
with n = 4, then
8
.
8
4
ln
2
4
.
24
2
ln
2
3
4 ≈
=
=
K
R
R
ƒ Note that I = VTln(n)/R3 ∝ VT, I is a
PTAT current
Brokaw Cell
ƒ Brokaw cell is commonly used bandgap-cell
li ti i it d i h i th fi
realization circuit and is shown in the figure
ƒ The function of op amp is replaced by Q3,
Q4 and Q5. Q3 and Q4 form a current mirror
to enforce the collector currents of Q1 and
Q2 are identical
ƒ The emitter follower Q5 raises the reference
voltage to Vref = (1+R1/R2)VBG

Stability of a Bandgap Reference
ƒ In a bandgap reference, there exists 2
feedback loops, 1 positive loop and 1
negative loop.
ƒ For the negative loop (the outer loop),
)
(
/
1
/
1
1
2
1
1
2
s
A
g
R
R
g
R
m
m
+
+
+
=
Gain
Loop
Negative
)
(
/
1
Gain
Loop
Negati e 1
2 s
A
g
R m
+
ƒ For the positive loop (the inner loop),
)
(
/
1
Gain
Loop
Negative
1
2
1
1
2 s
A
g
R
R
g
m
m
+
+
=
ƒ For stability, we must have a negative
)
(
/
1
/
1
Gain
Loop
Positive
1
1
1 s
A
g
R
g
m
m
+
=
loop gain magnitude > positive loop
gain magnitude. This is true as
((a+c)/(b+c))>(a/b) for b>a
Stability of Simple Brokaw Cell (1)
ƒ If we neglect R3, then clearly Q1 and Q2 form a differential pair with
positive and negative terminals tied together
p g g
ƒ Above is the way to break the loop for measuring loop gain. The
circuit should have a DC closed loop and AC open loop. The DC
closed loop is for biasing and the AC loop is to measure loop gain
p g p p g

Stability of Simple Brokaw Cell (2)
ƒ With the presence of R3, the positive loop looks like an amplifier with
degenerated emitter ⇒ the gain is smaller than that with R3.
Therefore, negative loop gain magnitude > positive loop gain
magnitude, i.e. stability requirement is satisfied
ƒ Cc is the compensation capacitor. Here, dominant pole
compensation is employed
compensation is employed
Overview
CMOS technologies

CMOS Bandgap References (1)
ƒ CMOS is the dominant technology for both digital and
analog circuit design nowadays
analog circuit design nowadays
ƒ Independent bipolar transistors are not available in
CMOS technology
ƒ CMOS voltage reference, however, can be achieved by
making use of the concept of voltage reference. These
CMOS circuits rely on using well transistors These
CMOS circuits rely on using well transistors. These
devices are vertical bipolar transistors that use wells
as their bases and the substrate as their collectors
ƒ These vertical bipolar well transistors have reasonable current gain
(≈ 25), but very high series base resistance (≈ 1kΩ/ ) due to the fact
that the base contact is far away from the base
that the base contact is far away from the base
ƒ The maximum collector current is thus limited to less than 0.1mA to
minimize errors due to the base resistance

Two possible implementations:
F l i th ll CMOS i l t ti h t i V f th
ƒ For example, in the n-well CMOS implementation, what is VBG of the
reference circuit?
ƒ Assume the op amp has very large gain
and very small input currents such that its
= +
2 2
BG EB R
V V V
and very small input currents such that its
input terminals are at the same voltage,
then EB
EB
EB
R V
V
V
V Δ
=
−
= 1
2
3
V V V V
ƒ Since the current through R1 is the same
as in R
= − = Δ
3 2 1
R EB EB EB
V V V V
as in R3
= = = Δ
3
1 1 1
1 3
1 3 3 3
or
R
R
R R EB
V
V R R
V V V
R R R R
1 3 3 3
R R R R
1
2
3
BG EB EB
R
V V V
R
= + Δ

CMOS Voltage References (5)
ƒ In CMOS realization, the bipolar
transistors are often taken the same
size, and different current densities
(IC/IS) are realized by taking R1 greater
than R2, which causes I2 to be greater
than I1:
2 1
1 2 1 1 2 2
1 2
or
R R
I R
V V I R I R
I R
= ⇒ = =
2
2 1
1
ln( )
EB EB EB
I
kT
V V V
q I
R R R R
kT
Δ = − =
1 1 1 1
2
3 2 3 2
ln( ) with ln( )
BG EB
R R R R
kT
V V K
R q R R R
⇒ = + =
Example
ƒ Find the resistances of a bandgap voltage reference based on the
CMOS n-well process where I1 = 5μA, I2 = 40μA and VEB = 0.65V at
300 1 2
T = 300K. Assume VBG = 1.24V
ƒ Ans. R1 = 118kΩ, R2 = 14.8kΩ and R3 = 10.1kΩ

Other CMOS References
ƒ Current mirror enforces equal
currents at M1, M2 and M3
ƒ Voltage clamping by M4 and M5
to enforce V1=V2
ƒ PTAT loop formed by Q1, Q2 and
R1
ln( )/
I V N R
=
ƒ Cascode current mirror or other
1
2
3
1
ln( )/
ln( )
T
ref EB T
I V N R
R
V V N V
R
=
= + ⋅
ƒ Cascode current mirror or other
forms for better current matching
at different supply voltages
Current Mirror with Op Amp
ƒ In CMOS reference using
current mirror with op amp,
an op amp is used to
enforce the drain voltage of
enforce the drain voltage of
M1 the same as of M2. This
allows a better current
matching of drain currents of
matching of drain currents of
M1 and M2

Error Sources in Voltage-Reference Design
ƒ Current mirror
ƒ Voltage-clamping circuit
Voltage clamping circuit
ƒ BJT emitter area ratio (BJT matching)
ƒ Resistor ratio (resistor matching)
Resistor ratio (resistor matching)
ƒ Base current
ƒ Base resistance
ƒ Base resistance
ƒ Systematic offset at different supply voltages
ƒ Random offset of devices
ƒ Random offset of devices
ƒ Temperature gradient within a chip
Design Considerations: BJTs
ƒ Closely packed common-centroid layout
L N d id i ifi h d h l i h
ƒ Large N does not provide significant change due to the logarithm
relation
ƒ Generally, N=8 is chosen based on chip area consideration

Design Considerations: Resistors
ƒ Matching is important to
obtain an accurate resistance
ratio
ƒ Square-like common-centroid
layout
layout
Typical Low-Voltage Implementation
ƒ Error-amplifier current mirror
enforces VA = VB
ƒ Min VDD = VREF + |Vov,M2|
ƒ Offset voltage → error
Offset voltage → error
ƒ Offset voltage = function of VTH,
mobility and transistor size →
mobility and transistor size →
temperature dependent
ƒ Use simple amplifier
p p
ƒ Reduce both systematic and
random offset

Offset Voltage Consideration
1
2
ln( )
( )[ ln( ) ]
T OFF
V N V
I
R
R
V V V N V
+
=
⇒ + +
A l N i d t i i i
2
2
1
( )[ ln( ) ]
ref EB T OFF
V V V N V
R
⇒ = + ⋅ +
ƒ A larger N is used to minimize
the required R2/R1, and the
effect of the amplifier offset
I hi
ƒ Increase chip area
Base Resistance Consideration
ƒ Large base resistance of
parasitic vertical BJT
ƒ Diode-connected BJT ≠ VEB
ƒ As mentioned before, I <
0.1mA
ƒ Not due to low-power
design, but due to reduce
voltage across RB
ƒ On layout, more N-well
contacts to reduce RB

Base Current Compensation
ƒ β is small in CMOS technology
ƒ IC ≠ IE and IC is a function of β
ƒ Introduced β in IC causes extra
errors and temperature
dependence
dependence
ƒ Base current compensation by a
dummy transistor Q1D
dummy transistor Q1D
ƒ IE of Q1 = I + I/β
I of Q1 = I
IC of Q1 = I
ƒ Q1D must match with Q1
Resistor Trimming
R i i b fi d b
ƒ Resistor ratio can be fine-tuned by
using a series of resistor network
associated with fuse
ƒ By burning the fuse, the resistor
value can be adjusted to fine-tune
th f lt d th
the reference voltage and the
temperature with zero tempco to a
particular value

Buffered Voltage Reference
ƒ Series-shunt feedback
Series shunt feedback
ƒ High output current to drive resistive load
ƒ Low output resistance
ƒ Isolation to reduce cross-talk through reference circuit
Current Source Generated by a Voltage
Reference
ƒ Series-series feedback
ƒ I = VREF/R
ƒ VMIN = Vov + VREF
MIN ov REF

CMOS Bandgap Reference with Sub-1-V
Operation (1)
ƒ R1 R2 & R3 of same material
3 2
2
2 1
( )( ( )ln( ) )
REF EB T
R R
V V N V
R R
= + ⋅
R1, R2 & R3 of same material
ƒ Good matching R1 and R2 for
optimizing tempco
optimizing tempco
ƒ Good matching R2 and R3 for
dj ti th l f V
adjusting the value of VREF
ƒ M1, M2 & M3 of equal W, L
ƒ VREF ≈ 0.5-0.7 V for matching VDS of
M1-M3 at different VDD
DD
CMOS Bandgap Reference with Sub-1-V
Operation (2)
ƒ Native NMOST : V = 0 2V
ƒ Native NMOST : VTHN = 0.2V
ƒ Not available in standard
CMOS technologies
CMOS technologies

Low-Voltage Design Problem of Error Amplifier
ƒ Worst case (smallest) VEB at
maximum operational
temperature
ƒ Worst case (largest) VEB and
|VTHP| at minimum temperature
temperature
ƒ VEB > VTHN + 2Vov
ƒ Low-VTHN (<0.4V) technology
B d ff t i V
| THP| p
ƒ VEB < VDD - |Vthp| - 2|Vov|
ƒ VDD(min) = VEB + |VTHP| + 2Vov
ƒ Body effect increases VTHN
References
ƒ H. Banba, et. al. “A CMOS bandgap reference circuit with sub-1-V
operation,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 670-
674, May 1999.
ƒ K. N. Leung, et. al. “A sub-1-V 15-ppm/°C CMOS bandgap voltage
reference without requiring low threshold voltage device,” IEEE
Journal of Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.
ƒ P. K. T. Mok, et. al. “Design considerations of recent advanced low-
voltage low-temperature-coefficient CMOS bandgap voltage
reference,” IEEE Custom Integrated Circuits Conference, Sep. 2004,
pp. 635-642.

EE6378 Bandgap Voltage Reference Circuit

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