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Energy Core Ecx - 2000 Processor
1.
2. Introduction
• Calxeda (previously known as Smooth-Stone) was a
company that aimed to provide computers based on the
ARM architecture for server computers.
• Calxeda claimed reduced energy consumption as well
as better cost per throughput, compared to x86-based
server manufacturers.
• Calxeda, has launched its second generation of chips
with the promise of up to twice the performance.
3. ECX-2000
Calxeda has announced its second generation SoC, the
ARM® Cortex™ A15 based Energy Core™ ECX-2000.
Using the ARM Cortex A15 quad-core processor, the
ECX-2000 delivers twice the performance, three times the
memory bandwidth, and four times the memory capacity
of the ground-breaking ECX-1000.
ECX-2000 uses standard ARM Cortex™-A15 cores up to
1.8 GHz, with the integrated Calxeda Fleet Fabric, 10Gb
Ethernet, and standard I/O controllers."
4. Continue..
The ECX-2000 also delivers the power efficiency of
ARM® processors, and the Open Stack, Linux, and
virtualization software needed for modern cloud
infrastructures.
In addition to enhanced performance, the ECX-2000
provides hardware virtualization support via KVM and
Xen hypervisors.
The Fleet Fabric enables the highest network and
interconnect bandwidth in the Micro Server space, making
this an ideal platform for streaming media and network-
intensive applications.
5. ECX-2000 processes data in 32-bit chunks but it have 40-
bit virtual memory addressing so the resulting server node
can support up to 16 GB of main memory.
While the Cortex-A15 cores can push up to 2.5 GHz,
Calxeda topped them out at 1.8 GHz to keep the thermal
envelope down.
ECX-2000 chip had four cores, and it was etched using
well-established 40 nanometer manufacturing processes
from Taiwan Semiconductor Manufacturing Corp.
6.
7. A15 is basically based on ARMv7, 32 bit CPU with 40 bits
Physical Addressing.
L1 instruction cache that is a 32 KB 2-Way set associative cache
with 64 bytes cache lines and optional parity protection per 16
bits (ECC protection per 32 bits for Data cache).
L2 cache is of 512KB, 1MB, 2MB or 4MB configurable size, 16
Way-set associative cache with optional ECC protection per 64
bits.
NEON data Engine is the implementation of the Advance single
instruction multiple data (SIMD) extension to ARMv7-A
Architecture.
8.
9.
10. Each 32-bit chip consists of a four-core ARM Cortex-A15
package clocked from 1.1GHz to 1.8GHz, along with a dual-core
ARM Cortex-A7 processor for management services, a broad set
of I/O controllers, 10Gbps Ethernet and a beefy 4MB L2 cache.
One of the A7 cores handles system and power management and
remote control capabilities, while the other can be programmed
by enterprises to suit their requirements.
11. Each core on the ECX-2000 has 32 KB of L1 instruction cache
and 32 KB of L1 data cache. The ECX-2000 has 4 MB of L2
cache shared across the four cores. These are exactly the same L1
and L2 cache sizes as used in the prior ECX-1000 chips.
Using Fleet Engines, reduce SoC cost. These engines control
the topology of the Fleet Services fabric, which can be set up
in 2D torus, mesh, butterfly tree, and fat tree network
configurations.
12.
13. • Start with four Server Nodes
• Consumes only 20W total power
• Connected via distributed fabric switches
• Connect up to 4 SATA drives per node
• Then scale this to thousands of Server Nodes
A small Calxeda Cluster
1. OpenStack is a free and open-source software platform for cloud computing, OpenStack is a set of software tools for building and managing cloud computing platforms for public and private clouds. Backed by some of the biggest companies in software development and hosting, as well as thousands of individual community members, many think that OpenStack is the future of cloud computing.
2. Coupled with certified support for Ubuntu 13.10 and the Havana Open stack release, this marks the first time an ARM SoC is ready for Cloud computing.
ECC: Error correction code.
3. It provide support for integer and floating point vector operations. This technology extends the processor functionality to provide support for the advance SIMDv2 instruction set.
On-chip Fabric Switch connects SoCs through low-latency 10Gb links
On-chip Management Engine provides out-of-band systems management capabilities while simultaneously governing power policies and optimizing network fabric routing
Integrated high-performance interfaces such as memory controllers with full ECC support and I/O subsystems for local SATA 2.0 ports and PCIe 2.0 support
ECX-2000 series SoC will be used in efficient data centers, web server farms, mid-tier application servers, content distribution networks, cloud storage, and emerging “Big Data” analytics.
Ethernet is a family of computer networking technologies commonly used in local area networks (LANs) and metropolitan area networks (MANs). It was commercially introduced in 1980 and first standardized in 1983 as IEEE 802.3, and has since been refined to support higher bit rates and longer link distances.
XAUI: Extended Auxiliary Unit Interface (XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the media access control and PHYSICAL layer of 10 Gigabit Ethernet (10GbE). XAUI is pronounced "zowie", a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface".)
SGMII: Serial Gigabit Media Independent Interface(The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet media access controls and PHYSICAL layers defined by Cisco Systems. It replaces the classic 22-wire GMII connection with a low pin count, 4-pair, differential SGMII connection.)
1. The Calxeda Fleet Fabric enables our customers to create an extremely efficient computing infrastructure that improves management of large-scale clouds at lower cost, lower power, and reduced carbon footprint. Coupled with the strength of our software and hardware partners, this is an unbeatable combination in an industry that is demanding better alternatives
2. This gives companies a greater degree of control over their chips and lets them increase the performance of base apps by offloading work to the SoC-bundled wimpy ARM core.
1. and ARM licensees are allowed to scale the L2 cache as they see fit ,