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Design Choices for Embedded Real-Time Control Systems<br />FPGA Camp, April 6, 2011<br />Endric Schubert, Missing Link Ele...
Real-Time Closed-Loop Control Systems<br />4/6/2011<br />2<br />FPGA Camp 2011<br />
Embedded Real-Time Control Systems- A Quadruple Whammy<br />Wide variety of I/O<br />Processing in Real-Time<br />Safety R...
Processing Steps in Real-Time Control Systems<br />4/6/2011<br />4<br />FPGA Camp 2011<br />An I/O connectivity problem<br...
Real-Time Processing on a Microcontroller<br />Like packet / video streaming … <br />BUT: must not loose any data!<br />4/...
Scalability Problems in Multi-Channel Systems<br />4/6/2011<br />6<br />FPGA Camp 2011<br />
Von Neumann Needs a Companion!<br />Sequential Processing with CPU<br />C, C++ Program<br />Parallel Processing with Logic...
Proposal: FPGA-Based Real-Time Control System<br />4/6/2011<br />8<br />FPGA Camp 2011<br />How to do:<br />I/O connectivi...
FPGA I/O Interfaces & Communication Peripherals<br />Covers almost all relevant I/O standards<br />And CommunicationInterf...
FPGA-Based Signal Conditioning<br />4/6/2011<br />10<br />FPGA Camp 2011<br />Today: Digital Signal Processing<br />Old Sc...
Closed-Loop PID Control<br />4/6/2011<br />11<br />FPGA Camp 2011<br />Courtesy: Dr. GiulioCorradi, Xilinx<br />
PID Control in an FPGA<br />Delay Optimized<br />Area Optimized<br />4/6/2011<br />FPGA Camp 2011<br />12<br />Zhao et al....
Scale-up Multi-Channel Control with Parallel Processing in the FPGA<br />4/6/2011<br />13<br />FPGA Camp 2011<br />
The Need to Run (Sequential) Software<br />4/6/2011<br />14<br />FPGA Camp 2011<br />
History Lesson: FPGAs Continue to Evolve to Meet Processing System Requirements<br />Co-processing<br />EmbeddedProcessing...
Yesterday’s FPGA Designs<br />Hardware-Centric Design Flow With FPGAs<br />4/6/2011<br />FPGA Camp 2011<br />16<br />
It's the Software, Dude!Embedded Processing Today<br />Software-Centric Design Flow With FPGAs<br />4/6/2011<br />FPGA Cam...
FPGA-to-CPU Connectivity<br />Companion Chips<br />Integrated Solutions<br />"A symbiosis of CPU and FPGA on one die to re...
A Convergence of Processing Solutions<br />General Purpose<br />Processors<br />FPGA Soft<br />Processors<br />ASSP<br />P...
A Convergence of Processing Solutions<br />Extensible<br />Processing<br />Platform<br />General Purpose<br />Processors<b...
Zynq-7000 Extensible Processing Platform<br /><ul><li>Complete ARM®-based Processing System
Dual ARM Cortex™-A9 MPCore™, processor centric
Integrated memory controllers & peripherals
Fully autonomous to the Programmable Logic
Tightly Integrated Programmable Logic
Used to extend Processing System
Scalable density and performance
Over 3000 internal interconnects
Flexible Array of I/O
Wide range of external multi-standard I/O
High performance integrated serial tranceivers
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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp

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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp. Endric Schubert, Missing Link Electronics
Glenn Steiner, Xilinx
Visit http://www.fpgacentral.com/fpgacamp for details

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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp

  1. 1. Design Choices for Embedded Real-Time Control Systems<br />FPGA Camp, April 6, 2011<br />Endric Schubert, Missing Link Electronics<br />Glenn Steiner, Xilinx<br />4/6/2011<br />1<br />FPGA Camp 2011<br />
  2. 2. Real-Time Closed-Loop Control Systems<br />4/6/2011<br />2<br />FPGA Camp 2011<br />
  3. 3. Embedded Real-Time Control Systems- A Quadruple Whammy<br />Wide variety of I/O<br />Processing in Real-Time<br />Safety Regulations<br />Device Obsolescence<br />4/6/2011<br />FPGA Camp 2011<br />3<br />
  4. 4. Processing Steps in Real-Time Control Systems<br />4/6/2011<br />4<br />FPGA Camp 2011<br />An I/O connectivity problem<br />Processing problem<br />Customization problem<br />Processing problem<br />Reliability problem<br />Another I/O Connectivity problem<br />
  5. 5. Real-Time Processing on a Microcontroller<br />Like packet / video streaming … <br />BUT: must not loose any data!<br />4/6/2011<br />FPGA Camp 2011<br />5<br />
  6. 6. Scalability Problems in Multi-Channel Systems<br />4/6/2011<br />6<br />FPGA Camp 2011<br />
  7. 7. Von Neumann Needs a Companion!<br />Sequential Processing with CPU<br />C, C++ Program<br />Parallel Processing with Logic Gates<br />VHDL, Verilog "Program"<br />4/6/2011<br />FPGA Camp 2011<br />7<br />Courtesy: Dr. Andre DeHon, UPenn<br />
  8. 8. Proposal: FPGA-Based Real-Time Control System<br />4/6/2011<br />8<br />FPGA Camp 2011<br />How to do:<br />I/O connectivity (read sensors, drive actuators)<br />Signal conditioning<br />Closed-loop control<br />
  9. 9. FPGA I/O Interfaces & Communication Peripherals<br />Covers almost all relevant I/O standards<br />And CommunicationInterfaces<br />4/6/2011<br />9<br />FPGA Camp 2011<br />
  10. 10. FPGA-Based Signal Conditioning<br />4/6/2011<br />10<br />FPGA Camp 2011<br />Today: Digital Signal Processing<br />Old School: Analog<br />
  11. 11. Closed-Loop PID Control<br />4/6/2011<br />11<br />FPGA Camp 2011<br />Courtesy: Dr. GiulioCorradi, Xilinx<br />
  12. 12. PID Control in an FPGA<br />Delay Optimized<br />Area Optimized<br />4/6/2011<br />FPGA Camp 2011<br />12<br />Zhao et al.: FPGA Implementation of Closed-Loop Control System for Small Scale Robot, IEEE, July 2005<br />
  13. 13. Scale-up Multi-Channel Control with Parallel Processing in the FPGA<br />4/6/2011<br />13<br />FPGA Camp 2011<br />
  14. 14. The Need to Run (Sequential) Software<br />4/6/2011<br />14<br />FPGA Camp 2011<br />
  15. 15. History Lesson: FPGAs Continue to Evolve to Meet Processing System Requirements<br />Co-processing<br />EmbeddedProcessing<br />ComplexControl<br />Increasing FPGA Capability<br />Processors tightly coupled <br />to FPGA fabric<br />enable extendibility with <br />co-processing to meet <br />real-time system requirements <br />Control<br />Logic<br />Glue<br />Logic<br />2011<br />1985<br />1990<br />1995<br />2000<br />4/6/2011<br />15<br />FPGA Camp 2011<br />
  16. 16. Yesterday’s FPGA Designs<br />Hardware-Centric Design Flow With FPGAs<br />4/6/2011<br />FPGA Camp 2011<br />16<br />
  17. 17. It's the Software, Dude!Embedded Processing Today<br />Software-Centric Design Flow With FPGAs<br />4/6/2011<br />FPGA Camp 2011<br />17<br />
  18. 18. FPGA-to-CPU Connectivity<br />Companion Chips<br />Integrated Solutions<br />"A symbiosis of CPU and FPGA on one die to reduce cost and PCB space!"<br />4/6/2011<br />18<br />FPGA Camp 2011<br />
  19. 19. A Convergence of Processing Solutions<br />General Purpose<br />Processors<br />FPGA Soft<br />Processors<br />ASSP<br />Processors<br />FPGA Hard<br />Processors<br />4/6/2011<br />19<br />FPGA Camp 2011<br />
  20. 20. A Convergence of Processing Solutions<br />Extensible<br />Processing<br />Platform<br />General Purpose<br />Processors<br />FPGA Soft<br />Processors<br />Memory<br />Interfaces<br />7 Series<br />ProgrammableLogic <br />ProcessingSystem<br />Common<br />Peripherals<br />Common Peripherals<br />Custom<br />Peripherals<br />ARM®<br />Dual Cortex-A9 MPCore™ System<br />Common Accelerators<br />Custom Accelerators<br />ASSP<br />Processors<br />FPGA Hard<br />Processors<br />4/6/2011<br />20<br />FPGA Camp 2011<br />
  21. 21. Zynq-7000 Extensible Processing Platform<br /><ul><li>Complete ARM®-based Processing System
  22. 22. Dual ARM Cortex™-A9 MPCore™, processor centric
  23. 23. Integrated memory controllers & peripherals
  24. 24. Fully autonomous to the Programmable Logic
  25. 25. Tightly Integrated Programmable Logic
  26. 26. Used to extend Processing System
  27. 27. Scalable density and performance
  28. 28. Over 3000 internal interconnects
  29. 29. Flexible Array of I/O
  30. 30. Wide range of external multi-standard I/O
  31. 31. High performance integrated serial tranceivers
  32. 32. Analog-to-Digital Converter inputs</li></ul>Memory<br />Interfaces<br />7 Series<br />ProgrammableLogic <br />ProcessingSystem<br />Common<br />Peripherals<br />Common Peripherals<br />Custom<br />Peripherals<br />ARM®<br />Dual Cortex-A9 MPCore™ System<br />Common Accelerators<br />Custom Accelerators<br />Software & Hardware Programmable<br />4/6/2011<br />21<br />FPGA Camp 2011<br />
  33. 33. Zynq-7000 Extensible Processing System<br />Processing System<br />Dynamic Memory Controller<br />DDR3, DDR2, LPDDR2<br />Static Memory Controller<br />Quad-SPI, NAND, NOR<br />Programmable<br />Logic:<br />System Gates,<br />DSP, RAM<br />AMBA® Switches<br />AMBA® Switches<br />2x SPI<br />ARM® CoreSight™ Multi-core & Trace Debug<br />2x I2C<br />NEON™/ FPU Engine<br />NEON™/ FPU Engine<br />2x CAN<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />2x UART<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />MIO<br />I/O<br />MUX<br />GPIO<br />512 KB L2 Cache<br />Snoop Control Unit (SCU)<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />ACP<br />2x SDIO<br />with DMA<br />Timer Counters<br />256 KB On-Chip Memory<br />DMA<br />General Interrupt Controller<br />Configuration<br />2x USB<br />with DMA<br />2x GigE<br />with DMA<br />AMBA® Switches<br />AMBA® Switches<br />PCIe<br />AMS<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />Multi Gigabit Transceivers<br />4/6/2011<br />22<br />FPGA Camp 2011<br />
  34. 34. Zynq-7000 EPP Processors<br />Processing System<br />Dynamic Memory Controller<br />DDR3, DDR2, LPDDR2<br />Static Memory Controller<br />Quad-SPI, NAND, NOR<br />Programmable<br />Logic:<br />System Gates,<br />DSP, RAM<br />AMBA® Switches<br />AMBA® Switches<br />2x SPI<br />ARM® CoreSight™ Multi-core & Trace Debug<br />2x I2C<br />NEON™/ FPU Engine<br />NEON™/ FPU Engine<br />2x CAN<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />2x UART<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />MIO<br />I/O<br />MUX<br />GPIO<br />512 KB L2 Cache<br />Snoop Control Unit (SCU)<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />ACP<br />2x SDIO<br />with DMA<br />Timer Counters<br />256 KB On-Chip Memory<br />DMA<br />General Interrupt Controller<br />Configuration<br />2x USB<br />with DMA<br />2x GigE<br />with DMA<br />AMBA® Switches<br />AMBA® Switches<br />PCIe<br />AMS<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />Multi Gigabit Transceivers<br />4/6/2011<br />23<br />FPGA Camp 2011<br />
  35. 35. Zynq-7000 EPP Memory Interfaces <br />Processing System<br />Dynamic Memory Controller<br />DDR3, DDR2, LPDDR2<br />Static Memory Controller<br />Quad-SPI, NAND, NOR<br />Programmable<br />Logic:<br />System Gates,<br />DSP, RAM<br />AMBA® Switches<br />AMBA® Switches<br />2x SPI<br />ARM® CoreSight™ Multi-core & Trace Debug<br />2x I2C<br />NEON™/ FPU Engine<br />NEON™/ FPU Engine<br />2x CAN<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />2x UART<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />MIO<br />I/O<br />MUX<br />GPIO<br />512 KB L2 Cache<br />Snoop Control Unit (SCU)<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />ACP<br />2x SDIO<br />with DMA<br />Timer Counters<br />256 KB On-Chip Memory<br />DMA<br />General Interrupt Controller<br />Configuration<br />2x USB<br />with DMA<br />2x GigE<br />with DMA<br />AMBA® Switches<br />AMBA® Switches<br />PCIe<br />AMS<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />Multi Gigabit Transceivers<br />4/6/2011<br />24<br />FPGA Camp 2011<br />
  36. 36. I/O Connectivity in Zynq-7000 EPP<br />Processing System<br />Dynamic Memory Controller<br />DDR3, DDR2, LPDDR2<br />Static Memory Controller<br />Quad-SPI, NAND, NOR<br />Programmable<br />Logic:<br />System Gates,<br />DSP, RAM<br />AMBA® Switches<br />AMBA® Switches<br />2x SPI<br />ARM® CoreSight™ Multi-core & Trace Debug<br />2x I2C<br />NEON™/ FPU Engine<br />NEON™/ FPU Engine<br />2x CAN<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />2x UART<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />MIO<br />I/O<br />MUX<br />GPIO<br />512 KB L2 Cache<br />Snoop Control Unit (SCU)<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />ACP<br />2x SDIO<br />with DMA<br />Timer Counters<br />256 KB On-Chip Memory<br />DMA<br />General Interrupt Controller<br />Configuration<br />2x USB<br />with DMA<br />2x GigE<br />with DMA<br />AMBA® Switches<br />AMBA® Switches<br />PCIe<br />AMS<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />Multi Gigabit Transceivers<br />4/6/2011<br />25<br />FPGA Camp 2011<br />
  37. 37. Agile Mixed Signal (AMS) for Data Acquisition<br />Processing System<br />Dynamic Memory Controller<br />DDR3, DDR2, LPDDR2<br />Static Memory Controller<br />Quad-SPI, NAND, NOR<br />Programmable<br />Logic:<br />System Gates,<br />DSP, RAM<br />AMBA® Switches<br />AMBA® Switches<br />2x SPI<br />ARM® CoreSight™ Multi-core & Trace Debug<br />2x I2C<br />NEON™/ FPU Engine<br />NEON™/ FPU Engine<br />2x CAN<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />2x UART<br />Cortex™-A9 MPCore™<br />32/32 KB I/D Caches<br />MIO<br />I/O<br />MUX<br />GPIO<br />512 KB L2 Cache<br />Snoop Control Unit (SCU)<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />ACP<br />2x SDIO<br />with DMA<br />Timer Counters<br />256 KB On-Chip Memory<br />DMA<br />General Interrupt Controller<br />Configuration<br />2x USB<br />with DMA<br />2x GigE<br />with DMA<br />AMBA® Switches<br />AMBA® Switches<br />PCIe<br />AMS<br />Multi-Standards I/Os (3.3V & High Speed 1.8V)<br />Multi Gigabit Transceivers<br />4/6/2011<br />26<br />FPGA Camp 2011<br />
  38. 38. Agile Mixed Signal (AMS) Processing<br /><ul><li>Dual 12-bit 1 Msps Analog-to-Digital Converters
  39. 39. ADCs carry out a 16-bit resolution conversion
  40. 40. Factory tested and specified 12-bit accuracy with 1V input range
  41. 41. Built in digital gain and offset correction / calibration
  42. 42. Dual Independent Track & Hold (T/H) Amplifiers
  43. 43. Separate Track/Hold amplifier ensures maximum throughput using multiplexed analog input channels
  44. 44. On-chip Voltage Reference
  45. 45. External reference input option
  46. 46. On-Chip Thermal and Supply Sensors
  47. 47. Flexible External Analog Inputs
  48. 48. Differential analog inputs with high common mode noise rejection
  49. 49. Support for unipolar, bipolar, and true differential input signal types </li></ul>4/6/2011<br />27<br />FPGA Camp 2011<br />
  50. 50. On-Chip and External Environmental Monitoring<br />Monitoring for higher reliability in industrial applications<br />Factory tested on-chip monitoring<br />Easier to implement than external solutionse.g., thermal diode monitor<br />Counter measures against physical attack / tampering in A&D<br />US government mandate: Cryptographic model must have built in counter measures against manipulation of power supplies and operating temperatures<br />Protection against reverse engineering and IP theft<br />Diagnostics for HW design and verification<br />Easy to use JTAG access with ChipScope support<br />Especially difficult to access places e.g., in enclosures / cabinets<br />JTAG<br />4/6/2011<br />28<br />FPGA Camp 2011<br />
  51. 51. Integrating It All Together:An Industrial Motor Control Application<br />4/6/2011<br />29<br />FPGA Camp 2011<br />
  52. 52. Put the Burden Where it Fits Best!<br />Extensible Processing Platforms<br />Allow optimum system partitioning between software and hardware<br />Build configurable systems that match your application!<br />4/6/2011<br />FPGA Camp 2011<br />Page 30<br />
  53. 53. Modern Implementation<br />4/6/2011<br />31<br />FPGA Camp 2011<br />Extensible Processing Platform<br />Memory<br />Interfaces<br />7 Series<br />ProgrammableLogic <br />ProcessingSystem<br />Common<br />Peripherals<br />Common Peripherals<br />Custom<br />Peripherals<br />ARM®<br />Dual Cortex-A9 MPCore™ System<br />Common Accelerators<br />Custom Accelerators<br />

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