Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition

1. Low-Complexity Digit-Serial Multiplier Over GF(2m)Based
on Efficient Toeplitz Block Toeplitz Matrix–Vector Product
Decomposition
ABSTRACT:
In this paper, we have shown that a regular Toeplitz matrix-vector product
(TMVP) can be transformed into a Toeplitz block TMVP (TBTMVP) using a
suitable permutation matrix. Based on the TBTMVP representation, we have
proposed a new (a , b)-way TBTMVP decomposition algorithm for implementing a
digit-serial multiplication. Moreover, it is shown that, based on iterative block
recombination, we can improve the space complexity of the proposed TBTMVP
decomposition. From the synthesis results, we have shown that the proposed
TBTMVP-based multiplier involves less area, less area–delay product, and higher
throughput compared with the existing digit serial multipliers. The proposed
architecture of this paper analysis the logic size, area and power consumption using
Xilinx 14.2.
SOFTWARE IMPLEMENTATION:
 Modelsim
 Xilinx ISE