High throughput finite field multipliers using redundant basis for fpga and asic implementations

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Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
High-Throughput Finite Field Multipliers Using
Redundant Basis for FPGA and ASIC
Implementations
Abstract—Redundant basis (RB) multipliers over Galois Field ( ) have gained
huge popularity in elliptic curve cryptography (ECC) mainly because of their
negligible hardware cost for squaring andmodular reduction. In this paper, we have
proposed a novel recursive decomposition algorithm for RB multiplication to
obtain high-throughput digit-serial implementation. Through efficient projection of
signal-flow graph (SFG) of the proposed algorithm, a highly regular processor-
space flow-graph (PSFG) is derived. By identifying suitable cut-sets, we have
modified the PSFG suitably and performed efficient feed-forward cut-set retiming
to derive three novel multipliers which not only involve significantly less time-
complexity than the existing ones but also require less area and less power
consumption compared with the others. Both theoretical analysis and synthesis
results confirm the efficiency of proposed multipliers over the existing ones. The
synthesis results for field programmable gate array (FPGA) and application
specific integrated circuit (ASIC) realization of the proposed designs and
competing existing designs are compared. It is shown that the proposed high-
throughput structures are the best among the corresponding designs, for FPGA and
ASIC implementation. It is shown that the proposed designs can achieve up to 94%
and 60% savings of area-delay-power product (ADPP) on FPGA and ASIC
implementation over the best of the existing designs, respectively.

SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com

International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

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About Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol. • Remote control: Parallel or serial interface. • Compatible with MAFI CCR system. • Compatible with IDM8000 CCR. • Compatible with Backplane mount serial communication. • Compatible with commercial and Defence aviation CCR system. • Remote control system for accessing CCR and allied system over serial or TCP. • Indigenized local Support/presence in India. • Easy in configuration using DIP switches. Technical Specifications Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol. Key Features Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol. • Remote control: Parallel or serial interface • Compatible with MAFI CCR system • Copatiable with IDM8000 CCR • Compatible with Backplane mount serial communication. • Compatible with commercial and Defence aviation CCR system. • Remote control system for accessing CCR and allied system over serial or TCP. • Indigenized local Support/presence in India. Application • Remote control: Parallel or serial interface. • Compatible with MAFI CCR system. • Compatible with IDM8000 CCR. • Compatible with Backplane mount serial communication. • Compatible with commercial and Defence aviation CCR system. • Remote control system for accessing CCR and allied system over serial or TCP. • Indigenized local Support/presence in India. • Easy in configuration using DIP switches.

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High throughput finite field multipliers using redundant basis for fpga and asic implementations

1. Logic Mind Technologies Vijayangar (Near Maruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations Abstract—Redundant basis (RB) multipliers over Galois Field ( ) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring andmodular reduction. In this paper, we have proposed a novel recursive decomposition algorithm for RB multiplication to obtain high-throughput digit-serial implementation. Through efficient projection of signal-flow graph (SFG) of the proposed algorithm, a highly regular processor- space flow-graph (PSFG) is derived. By identifying suitable cut-sets, we have modified the PSFG suitably and performed efficient feed-forward cut-set retiming to derive three novel multipliers which not only involve significantly less time- complexity than the existing ones but also require less area and less power consumption compared with the others. Both theoretical analysis and synthesis results confirm the efficiency of proposed multipliers over the existing ones. The synthesis results for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) realization of the proposed designs and competing existing designs are compared. It is shown that the proposed high- throughput structures are the best among the corresponding designs, for FPGA and ASIC implementation. It is shown that the proposed designs can achieve up to 94% and 60% savings of area-delay-power product (ADPP) on FPGA and ASIC implementation over the best of the existing designs, respectively.

2. SOFTWARE REQUIREMENT:  ModelSim6.4c.  Xilinx 9.1/13.2. HARDWARE REQUIREMENT:  FPGA Spartan 3. PROJECT FLOW: First Review: Literature Survey Paper Explanation Design of Project Project Enhancement explanation Second Review: Implementing 40% of Base Paper Third Review Implementing Remaining 60% of Base Paper with Future Enhancement (Modification) For More Details please contact Logic Mind Technologies Vijayangar (NearMaruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Mail: logicmindtech@gmail.com

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