Galeshwar Joriga is seeking a career in VLSI design and verification. He has a Master's degree in VLSI and Bachelor's degree in ECE. He has over 1 year of hands-on experience in RTL design using Verilog HDL and tools like Synopsys. Some of his projects include FSM design, synchronous FIFO, ALU, and Fibonacci series. His M.Tech project involved implementing a low area multiplexer-based CORDIC algorithm. He also has 3 months of internship experience verifying an IIR filter using Verilog HDL, C, and Perl.

1. GALESHWAR JORIGA
Call: +91 9849815804
 E-mail: ganeshsri411@gmail.com
Present Address:
Marathahalli,
Bangalore,
Karnataka– 560038.
Permanent Address:
H No: 8-120/2,
Damaracherla Village,
Damaracherla Mandal,
Nalgonda(Dist),
AP – 507 209.
Credentials:
 Have good knowledge in C
programming and oops concepts.
 Knowledge in High level Register
Transfer Level (RTL) language such
as VerilogHDL.
 Hands on experience Verilog and
SystemVerilog on Simulation and
synthesis tool.
 Possess strong verification skills like
random and advertisings testing as
well as debugging.
 In-depth knowledge of debug tools,
logic design concepts and simulators
like Modelsim and VCS simulator.
 Good understanding of Synthesis,
Static Timing Analysis (STA) using
DC compiler Synopsys.
 Ability to write TCL script for setup
files in DC compiler.
 Good knowledge on DFT & Computer
Architecture.
CAREER OBJECTIVE
To build a career with a dynamic and professionally managed
organization that provide ample opportunities for growth in the
field of VLSI so as to reflect high standard of performance in all
assignments, thereby ensuring organizational and personal growth.
* EDUCATION
Master Of Technology (VLSI) – 2013-15
JNT-UNIVERISITY (SEER AKADEMI) – 76.3%, JNTU, ANANTHAPUR.
Bachelor of Technology (E.C.E.) – 2008 - 2012
SREE DATTHA INSTITUTIONS – 71.15%,JNTU, HYDERABAD.
Intermediate (MPC) – 2006 - 2008
NALANDA JUNIOR COLLEGE – 86.80%
BOARD OF INTERMEDIATE EDUCATION.
SSC (10th Standard) – 2006
NAGARJUNA HIGH SCHOOL – 77.50%
BOARD OF SECONDARY EDUCATION.
* TECHNICAL SKILLS
Programming Languages : ‘C’, OOPS, VerilogHDL.
VLSI EDA Tools : ModelSim,
Synopsys(VCS Simulator, DC Compiler)
Cadence(NCSim).
HVL : System Verilog. ( UVM )
Operating Systems : Linux, Windows.
Scripting : Pearl, and basics of Tcl and Python.
*PROFESSIONAL EXPERIENCE
 Worked on different projects from design to verification
 Good understanding of the ASIC and FPGA design flow and
Digital Design.
 Having 1 YEAR hands on Practical Experience on RTL
coding with Verilog HDL Using Synopsys EDA Tool.
 Having 3 months Real Time Industrial Internship
Experience on Functional Verification on IIRFILTER.
*SUMMARY
Worked in all concepts of VLSI design and verification,
MODULES WORKED ON: All basic combinational and
sequential Digital designs, Different types of FSMs, memory
designs and verification, FIFO, ALU.

2. PROJECTS WORKED:
1. FSM Design
2. Synchronous FIFO
3. ALU
4. Fibonacci Series
Role: Design and Verification.
HDL & HVL: Verilog HDL & System Verilog.
EDA Tools: Synopsys (VCS Simulator, DC compiler).Cadence (NC simulator).
1. Understanding the Specification.
2. Preparation of Verification Plan.
3. Identification of Test cases, Verification Plan review and modification.
4. Preparation of Test cases.
5. Written the Reference model in C language.
6. TB coding and debugging simulation failures.
7. Code and Functional Coverage.
8. Create a Make file for compilation.
M.TECH PROJECT:
Title : Low Area Multiplexer Based Using CORDIC.
CORDIC algorithm is an iterative method of performing vector rotations by arbitrary angles
using shifts, addition and subtraction. In the rotation mode, CORDIC may be used for converting a
vector in polar form to rectangular form. In the vector mode, it converts a vector in rectangular form to
polar form. Even though adders and shifters were originally used for the implementation of CORDIC. In
this scheme, the first stage is removed and adders at the 2nd and 3rd stages are replaced by multiplexers.
LANGUAGE USED : VERILOG HDL, TCL.
INTERNSHIP WORK:
Title: IIR Filter Verification Using Verilog HDL.
IIR FILTER mainly used in the Analog to Digital conversion in Digital signal processing.
Using fixed point representation and performs the Addition and Multiplication and Rounding
mechanism.
LANGUAGE USED : VERILOG HDL, C, PERL.

3. * EXTRACURRICULAR ACTIVITIES
 Participated in ARM processors work shop conducted by Central Gov. ATIEPI.
 Participated in VLSI design workshop conducted by Central Gov. IETE.
 Served as Captain for ECE department Kabaddi Team in Graduation.
 Active participant in organizing technical events held at our college.
 Organized the Cultural event for ECE Subhiksha in our college.
* HOBBIES
 Playing Kabaddi .
 Solving Rubik’s cube 3x3.
 Playing cricket.
* PERSONAL INFORMATION
Father's Name : Srinivasa Rao
Gender : Male.
Nationality : Indian.
Marital Status : Single.
Languages : English, Hindi, Telugu.
* DECLARATION
I hereby declare that the information furnished above is true to the best of my Information
knowledge belief.
Place :
Date : (J. Galeshwar)