1. Kishor S
Tel no: (+91) 9788095572
Email:kishoresec14@rediffmail.com
To secure a challenging position where I can effectively contribute my skills as a design
Engineer in VLSI domain, possessing competent Technical Skills to achieve the target of
the company inline with my co-workers.
PROFESSIONAL SYNOPSIS
 A result oriented professional with 1 year seven moths experience in the area of RTL
Design.
 Proficiency in languages like VHDL, Verilog HDL and C
 Having the knowledge communication protocols like UART, RS232, USB 2.0, SPI, I2C,
and encryption Algorithm AES.
 Proficiency in tools like Tanner EDA V14.1, Xilinx ISE 14.1, Xilinx System Generator
and Altera FPGA Design Tools.
 Handled projects Real Time Clock, Dual Port RAM, Green Crop
 Involved in FPGA Board Development.
ORGANIZATIONAL EXPERIENCE
 Working as a VLSI Project Engineer in Vee Eee TECHNOLOGIES solution Pvt Ltd,
Chennai from August 2013 to till date.
SUMMARY OF QUALIFICATIONS
 Experience in writing RTL models in Verilog HDL Test benches
 Very good knowledge in Tanner EDA Tool.
 Good understanding of ASIC and FPGA design flow.
 Good understanding of Digital Electronics and Digital Design methodologies.
 Experience in industry standard EDA tools for the front-end design.
Notable Accomplishments
 Independent and self-motivated
 Committed to deadlines and schedules
Key projects handled
Title: Green Crop
SKILL SETS: VHDL, Xilinx Design Tools
Contribution:
 Develop the Clock and control signals for CCD Image sensor.
 Develop the Color sorting Algorithm.
 Develop the interface model for HMI.
 Develop the test bench for all above modules.

2. Description:
GREEN CROP sets standards in the grain milling industry. Its processing systems with
capacities ranging from 2 to 10 metric tons per hour guarantee maximum yields of outstanding
quality with minimum product breakage.
Title: Real Time Clock – RTL design
SKILL SETS: Verilog, Modelsim , Xilinx Design Tool
Contribution:
 Design of Real Time Clock using Verilog HDL independently.
 Simulated the RTL model using Modelsim.
 Synthesized the design.
Title: Dual Port RAM – RTL design
SKILL SETS: Verilog, Modelsim , Xilinx Design Tool
Contribution:
 Design of Dual Port RAM using Verilog HDL independently.
 Simulated the RTL model using Modelsim.
 Synthesized the design.
Academic project:
Title: FPGA implementation of Efficient VLSI Architecture for Multiplier
Description: Design of Modified Booth Multiplier done in VHDL
Co-Curricular Activities:
Paper Presentation:
 Presented a paper on “CELL PHONE SENSOR SYSTEM TO PREVENT NUCLEAR
TERRORISM” in Arunai Engineering College, Thiruvannamalai.
Membership:
 An Active Member of “ The Institution of Electronics and Telecommunication
Engineers” (IETE) Forum
Scholastic Credentials
 Bachelor of Engineering in Electronics and Communication Engineering, Erode
Sengunthar Engineering College, Anna University, 7.91 CGPA, 2013.
 H.S.C, Govt. Higher Secondary School, Kalambur, 88.6%, 2009.
 SSLC, Govt.Higher Secondary School, Kalambur, 85%, 2007.
IT SKILL SET
Languages:
C, VHDL, Verilog HDL.
Tools:
Xilinx, Altera Design Tools, Tanner EDA and Modelsim.
Protocols:
I2C, SPI, UART, USB 2.0, RS232 and AES

3. Personal Details:
Date of Birth : 4th July 1992
Languages Known : English, Tamil
Father’s Name : M.selvaraj
Mailing Address : 2/84, Perumal Koil Street, Kalambur-606903
Date:
Place:
S.Kishor