3rd version of division algorithm

1. TO
OUR PRESENTATION

2. PORT CITY
INTERNATIONAL
UNIVERSITY,
CHITTAGONG
CSE-13BATCH (A)

3. OUR GROUP NAME:-
TEAM RATIO
PRESENTED BY-
1.Farhan Nasir (CSE013 06125)
2.Thirtha Das (CSE013 06136)

4. OUR TOPIC:-
Final Version of the Division
Algorithm and Hardware

5. DIVISION:
Quotient1
10010101000
-1000
Dividend
• Divisor
10
101
1010
-1000
10 Reminder
Won’t go
Won’t go
001

6. 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg,
(32-bit Quotient reg)

7. Divide Algorithm
Version 3:
3b. Restore the original value by adding the Divisor
register to the left half of the Remainder register,
&place the sum in the left half of the Remainder
register. Also shift the Remainder register to the
left, setting the new least significant bit to 0.
Test
Remainder
Remainder < 0Remainder  0
2. Subtract the Divisor register from the
left half of the Remainder register, & place the
result in the left half of the Remainder register.
3a. Shift the
Remainder register
to the left setting
the new rightmost
bit to 1.
1. Shift the Remainder register left 1 bit.
Done. Shift left half of Remainder right 1 bit.
Yes: n repetitions (n = 4 here)
nth
repetition?
No: < n repetitions
Start: Place Dividend in Remainder
Divided 810 by 310
Dividend = 10002
Divisor = 00112
Reminder = 000010002

8. Iteration Step Divisor Remainder
Divide 710 = 01112 (Dividend) by 210 = 00102 (Divisor)
Quotient = 00112 = 310
Remainder = 00012 = 110
0000
-0010
1110
Shift left half of Rem right 1 0010 0001 0011
3a. Rem>=0 sft L, R0=1 0010 0010 0011
4 2. Rem = Rem – Div 0010 0001 0001
3a. Rem>=0 sft L, R0=1 0010 0011 0001
3 2. Rem = Rem – Div 0010 0001 1000
3b.Rem<0 +Div, sft L,R0=0 0010 0011 1000
2 2. Rem = Rem – Div 0010 1111 1100
3b.Rem<0 +Div, sft L,R0=0 0010 0001 1100
1 2. Rem = Rem – Div 0010 1110 1110
Shift remainder left 1 0010 0000 1110
0 Initial values 0010 0000 0111
0001
-0010
1111
0011
-0010
0001
0011
-0010
0001
1110 1110
+0010
0000 1110
1111 1100
+0010
0001 1000