Algorithmic State Machines (ASMs): ASM chart, ASM block, simplifications and timing considerations with design example. ASMD chart for binary multiplier and Verilog HDL code, one hot state controller. Asynchronous Sequential logic: Analysis procedure-Transition table, flow table, race conditions. Hazards with design example of Vending-Machine Controller

1. MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL SYSTEM DESIGN WITH VERILOG
FACULTY NAME: Mrs. B. Indira Priyadarshini
MATRUSRI
ENGINEERING COLLEGE

2. INTRODUCTION:
Asynchronous sequential circuits are discussed. While this treatment is not
exhaustive, it provides a good indication of the main characteristics of such
circuits. Even though the asynchronous circuits are not used extensively in
practice, they should be studied because they provide an excellent vehicle for
gaining a deeper understanding of the operation of digital circuits in general.
They illustrate the consequences of propagation delays and race conditions that
may be inherent in the structure of a circuit.
UNIT-IV
OUTCOMES:
After successful completion of this Unit students should be able to
Solve ASM for simple application
Design asynchronous sequential logic circuits
Designing of Vending machine controller
MATRUSRI
ENGINEERING COLLEGE

3. CONTENTS:
ASM chart
ASM block
Simplifications and timing considerations with design example.
OUTCOMES:
Students will be able to design algorithmic state machines.
MODULE-I: ALGORITHMIC STATE
MACHINES (ASMs)
MATRUSRI
ENGINEERING COLLEGE

4. ASM
MATRUSRI
ENGINEERING COLLEGE
The design of the logic of a digital system can be divided into two distinct
efforts.
One part is concerned with designing the digital circuits that perform the
data‐processing operations.
The other part is concerned with designing the control circuits that
determine the sequence in which the various manipulations of data are
performed.

5. ASM Chart
MATRUSRI
ENGINEERING COLLEGE
ASM chart resembles a conventional flowchart describes the sequence of
events, i.e., the ordering of events in time, as well as the timing relationship
between the states of sequence controller and the events that occur while
going from one sate to the next.
An ASM chart is composed of three basic elements:
State box: Conditional box:
Decision box:

6. Example
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Moore Model: Mealy Model:

7. ASM Block
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An ASM block is a structure consisting of one state box and all the decision
and conditional boxes connected to its exit path.
An ASM block has one entrance and any number of exit paths represented by
the structure of the decision boxes.
An ASM chart consists of one or more interconnected blocks.
Example:

8. Simplifications
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State diagram equivalent to the ASM chart:
Decision box can be simplified by labelling only the edge corresponding to
the asserted decision variable and leaving the other edge without a label.
A further it omits the edges corresponding to the state transitions that occur
when a reset condition is asserted.
•Output signals that are not asserted are not shown on the chart.
•Presence of the name of an output signal indicates that it is asserted.

9. Timing Considerations
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Transition between states:
The timing for all registers and flip‐flops in a digital system is controlled by a
master‐ clock generator.
The clock pulses are applied not only to the registers of the datapath, but
also to all the flip‐flops in the state machine implementing the control unit.

10. 1. While converting a FSM state diagram to an ASM chart, every FSM state
will map into an ASM Block.
2. What are the three basic elements in an ASM chart?
Ans: State Box, Decision Box, Conditional box
3. Difference in conventional flowchart and ASM chart is time relationship.
4. State box without decision and conditional box is simple block.
5. In ASM design flip-flops are considered to be positive edge triggered.
Questions & Answers
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ENGINEERING COLLEGE

11. CONTENTS:
Binary Multiplier
OUTCOMES:
Students will be able to design ASMD chart for Binary multiplier.
MODULE-II: ASMD Chart
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12. ASMD Chart
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An ASMD chart differs from an ASM chart in three important ways:
•Does not list register operations within a state box.
•The edges of an ASMD charts are annotated with register operations that
are concurrent with the state transition indicated by the edge.
•Includes conditional boxes identifying the singles which control the register
operation s that annotate the edges of the chart.
•Associates register operations with state transitions rather than with state.
Designed an ASMD chart have three-step:
•Form an ASM chart displaying only how the inputs to the controller
determine its state transitions.
•Convert the ASM chart to an ASMD chart by annotating the edges of ASM
chart to indicate to the concurrent register operations of the datapath unit.
•Modify the ASMD chart to identify the control singles that are generated by
the controller and the ca use the indicated register operations in the
datapath unit.

13. Binary Multiplier
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Let us multiply the two binary numbers 10111 and 10011:
23 10111 multiplicand
19 10011 multiplier
10111
10111
00000
00000
10111
437 110110101 product
The product obtained from the multiplication of two binary numbers of n bits
each can have up to 2n bits.

14. Binary Multiplier
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Block diagram:
Datapath:

15. ASMD Chart for Binary Multiplier
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The intermediate form annotates the
ASM chart of the controller with the
register operations.
The completed chart identifies the
Moore and Mealy outputs of the
controller.

16. Example
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Multipicand B = 101112 = 17H = 2310 Multiplier Q = 100112 = 13H = 1910
C A Q P
Multiplier in Q
Q0 = 1; add B
First partial product
Shift right CAQ
Q0 = 1; add B
Second partial product
Shift right CAQ
Q0 = 0; shift right CAQ
Q0 = 0; shift right CAQ
Q0 = 1; add B
Fifth partial product
Shift right CAQ
Final product in AQ = 01101101012 = 1b5H
0
0
0
1
0
0
0
0
0
00000
10111
10111
01011
10111
00010
10001
01000
00100
10111
11011
01101
10011
11001
01100
10110
01011
10101
101
100
011
010
001
000

17. Control Logic
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Design of digital system
•Register transfer in the datapath unit
•Control logic of the control unit
Must execute two steps when implementing the control logic:
(1) establish the required sequence of states, and
(2) provide signals to control the register operations.
State Transition Register Operations
From To
S_idle
S_idle S_add
S_add S_shift
S_shift
Initial state
A <= 0, C <= 0, P <= dp_width
P <= P-1
if (Q[0]) then (A <= A+B, C <= Cout)
shift right [CAQ], C <= 0

18. Sequence Register and Decoder
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•Uses a register for the control states and a decoder to provide an output
corresponding to each of the states.
•A register with n flip‐ flops can have up to 2n states, and an n ‐to‐ 2n ‐line
decoder has up to 2n outputs.
•An n ‐bit sequence register is essentially a circuit with n flip‐flops, together
with the associated gates that effect their state transitions.
Present-State
Symbol
Present
State
Inputs Next
State
G1 G0 Start Q[0] Zero G1 G0
Ready
Load_regs
Decr_P
Add_regs
Shift_regs
S_idle
S_idle
S_add
S_add
S_shift
S_shift
0 0
0 0
0 1
0 1
1 0
1 0
0 X X
1 X X
X 0 X
X 1 X
X X 0
X X 1
0 0
0 1
1 0
1 0
0 1
0 0
1 0 0 0 0
1 1 0 0 0
0 0 1 0 0
0 0 1 1 0
0 0 0 0 1
0 0 0 0 1

19. Logic Diagram
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Logic diagram of control for binary multiplier using a sequence register and
decoder

20. Logic Diagram
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•DG1 = G0Start + G2Zero’
•DG2 = G1

21. 1. ASMD chart represents a partition of a complex digital machine into its
datapath and control units.
2. An ASMD chart does not list register operations within a state box.
3. An ASMD chart associates register operations with state transitions
rather than with states.
4. The operations of addition and shifting are executed by the Binary
Multiplier.
Questions & Answers
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ENGINEERING COLLEGE

22. CONTENTS:
Binary Multiplier
One hot design
Verilog Code
OUTCOMES:
Students will be able to design and write a code for Binary multiplier.
MODULE-III: One hot Controller
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ENGINEERING COLLEGE

23. One‐Hot Design
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One Flip‐Flop per State
Disadvantages:
•Uses the maximum number of flip‐flops
•Increase system cost
•No state or excitation tables are needed
Advantages:
•Offers a savings in design effort
•Increase in operational simplicity
•Decrease in the total number of gates, since a decoder is not needed.
Present-
State Symbol
Present
State
Inputs Next State
G2 G1 G0 Start Q[0] Zero G2 G1 G0
Ready
Load_regs
Decr_P
Add_regs
Shift_regs
S_idle
S_idle
S_add
S_add
S_shift
S_shift
0
0
0
0
1
1
0 1
0 1
1 0
1 0
0 0
0 0
0 X X
1 X X
X 0 X
X 1 X
X X 0
X X 1
0
0
1
1
0
0
0 1
1 0
0 0
0 0
1 0
0 1
1 0 0 0 0
1 1 0 0 0
0 0 1 0 0
0 0 1 1 0
0 0 0 0 1
0 0 0 0 1

24. Logic Diagram
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DG0 = G0Start’ + G2Zero
DG1 = G0Start + G2Zero’
DG2 = G1

25. Verilog Code
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module Binary_Multiplier (Product, Ready, Multiplicand, Multiplier, Start,
clock, reset_b);
// Default configuration: five-bit datapath
parameter dp_width = 5; // Set to width of datapath
output [2*dp_width -1: 0] Product;
output Ready;
input [dp_width -1: 0] Multiplicand, Multiplier;
input Start, clock, reset_b;
parameter BC_size = 3; // Size of bit counter
parameter S_idle = 3'b001, // one-hot code
S_add = 3'b010,
S_shift = 3'b100;
reg [2: 0] state, next_state;
reg [dp_width -1: 0] A, B, Q; // Sized for datapath
reg C;
reg [BC_size -1: 0] P;
reg Load_regs, Decr_P, Add_regs, Shift_regs;

26. Verilog Code
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// Miscellaneous combinational logic
assign Product = {A, Q};
wire Zero = (P == 0); // counter is zero
// Zero = ~|P; // alternative
wire Ready = (state == S_idle);
// controller status
// control unit
always @ ( posedge clock, negedge reset_b)
if (~reset_b)
state <= S_idle;
else
state <= next_state;
always @ (state, Start, Q[0], Zero)
begin
next_state = S_idle;
Load_regs = 0; Decr_P = 0; Add_regs = 0;
Shift_regs = 0;
case (state)
S_idle: begin
if (Start) next_state = S_add;
Load_regs = 1;
end
S_add: begin
next_state = S_shift;
Decr_P = 1;
if (Q[0]) Add_regs = 1;
end
S_shift: begin
Shift_regs = 1;
if (Zero) next_state = S_idle;
else next_state = S_add;
end
default : next_state = S_idle;
endcase
end

27. Verilog Code
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ENGINEERING COLLEGE
// datapath unit
always @ ( posedge clock) begin
if (Load_regs) begin
P <= dp_width;
A <= 0;
C <= 0;
B <= Multiplicand;
Q <= Multiplier;
end
if (Add_regs)
{C, A} <= A + B;
if (Shift_regs)
{C, A, Q} <= {C, A, Q} >> 1;
if (Decr_P)
P <= P -1;
end
endmodule

28. 1. The control signals govern the synchronous register operations of the
datapath.
2. The ASMD chart and the state diagram for the controller of the binary
multiplier have three states and two inputs.
3. The decoder is not needed if a one‐hot code is used.
4. The outputs of the decoder are used to generate the inputs to the
next‐state logic as well as the control outputs.
5. The outputs of the controller should be connected to the datapath to
activate the required register operations.
Questions & Answers
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ENGINEERING COLLEGE

29. CONTENTS:
Analysis procedure-
Transition table
Flow table
Race conditions
OUTCOMES:
Students will be able to
•learn analysis of asynchronous Sequential Circuits
•learn map, transition table and flow table
•Design of asynchronous Sequential Circuit
•Solve race conditions in asynchronous Sequential Circuit
MODULE-IV: Asynchronous Sequential
Circuits
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ENGINEERING COLLEGE

30. Asynchronous Sequential Circuit
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•It do not use clock pulses, so change of state occurs whenever input changes
•Memory element used are latch or time delay elements
•A combinational circuit with feedback is asynchronous sequential circuit

31. MATRUSRI
ENGINEERING COLLEGE
Transition table is useful to analyze an asynchronous circuit from the circuit
diagram. Procedure to obtain transition table:
1. Determine all feedback loops in the circuits
2. Assign excitation variable to output (Y ) that is fed-back
3. Assign secondary variable at the input (y ) where feedback ends
4. Derive the Boolean functions of all excitation variable (Y’s)
5. Plot each Y function in a map and combine all maps into one table (flow
table)
6. Circle those values of Y in each square that are equal to the value of y in the
same row (stable states)
Steps of Analysis

32. MATRUSRI
ENGINEERING COLLEGE
The state variables: Y1 and Y2
Y1 = xy1 + x′y2
Y2 = xy′1 + x′y2
Map for Y1 = xy1 +x′y2 Map for Y2 = xy′1 +x′y2
Transition Table
y1 y2
x
0 1
00 0 0
01 1 0
11 1 1
10 0 1
y1 y2
x
0 1
00 0 1
01 1 1
11 1 0
10 0 0

33. MATRUSRI
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•The transition table shows the value of Y = Y1Y2 inside each square. Those
entries where Y = y are circled to indicate a stable condition.
•Combine the internal state with input variables is the Total state of the circuit.
•Stable total states:
•y1y2x = 000, 011, 110 and 101
•unstable total states:
•y1y2x = 001, 010, 111, and 100
•If the input alternates between 0 and1, the circuit will repeat the sequence of
states:
Transition Table

34. MATRUSRI
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• A flow table is similar to a transition table except that the internal state are
symbolized with letters rather than binary numbers.
• Also includes the output values of the circuit for each stable state.
Flow Table

35. MATRUSRI
ENGINEERING COLLEGE
•To obtain the circuit by a flow table, it is necessary to convert the flow table
into a transition table by assignment of a distinct binary value to each state
from which derive the logic diagram.
Flow Table

36. MATRUSRI
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•Two or more binary state variables will change value when one input
variable changes.
Cannot predict state sequence if unequal delay is encountered.
•Non-critical race: The final stable state does not depend on the change
order of state variables
•Critical race: The change order of state variables will result in different
stable states. Must be avoided !!
Race condition

37. MATRUSRI
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• It can be solved by making a proper binary assignment to the state
variables.
•The state variables must be assigned binary numbers in such a way that
only one state variable can change at any one time when a state transition
occurs in the flow table.
Race Solution

38. MATRUSRI
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Asynchronous sequential circuits may oscillate between unstable states due
to the feedback
•Must check for stability to ensure proper operations
Can be easily checked from the transition table
•Any column has no stable states unstable
Ex: when x1 x2 =11 in (b), Y and y are never the same
Y=x2 (x1 y)’=x1’ x2 +x2 y’
Stability Check

39. 1. A flow table will define the state changes and outputs that must be
generated.
2. An excitation table will depict the transitions in terms of the state
variables.
3. Race condition is used to refer to as unpredictable behavior.
4. Non-critical race occur when the final stable state does not depend on the
change order of state variables
5. Asynchronous sequential circuits may oscillate between unstable states
due to the feedback
Questions & Answers
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ENGINEERING COLLEGE

40. CONTENTS:
Hazards in Combinational Circuits
Hazards in Sequential Circuits
Implementation with SR Latches
OUTCOMES:
Students will be able to design a glitch free circuit
MODULE-V: Hazards
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ENGINEERING COLLEGE

41. Hazards
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Hazards are unwanted switching transients that may appear at the output of a
circuit because different paths exhibit different propagation delays.
•Hazards occur in combinational circuits, may cause a temporary false-
output value.
•Hazards occur in asynchronous sequential circuits, result in a transition
to a wrong stable state.
Hazards in combinational circuits:
Static -1 Hazard:
The output go to 0 when it should remain a 1.
Static -0 Hazard:
The output may momentarily go to 1 when it should remain 0.
Dynamic Hazard:
Causes the output to change 2 or 3 time when it should be change
from 1 to 0 or 0 to 1

42. Hazards in Combinational Circuits
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Circuit with a static hazard:
Y = x1x2 + x2′x3
Y = x1x2 + x2′ x3 + x1x3
Hazard free Circuit: To eliminate a hazard is to enclose the two minterms in
question with another product term that overlaps both groupings.
Y = x1x2 + x2′ x3 + x1x3

43. Hazards in Sequential Circuits
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•A glitch here cause the circuit to enter an incorrect state and possibly become
stable in that state. Therefore, the circuitry that generates the next-state
variables must be hazard free.
Y = x1x2 + x2′y
•Can be eliminated by adding an extra gate.

44. Implementation with SR Latches
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•An alternative way to avoid static hazards is to realize the asynchronous
sequential circuit with SR latches.
S = (AB + CD) ′ = (AB) ′ (CD) ′
R = (A′C) ′
Q = (Q′S) ′ = [Q′ (AB) ′ (CD) ′]
•Generated with two levels of NAND gates:
Essential Hazards is the result of the effects of a single input variable change
reaching one feedback path before another feedback path.
•Cannot be corrected by adding redundant gates.
•Eliminated by the insertion of sufficient delays in the feedback paths.

45. 1. When the output goes to 0, then temporarily moves to 1 and 0, before
stabilizing to 1, Dynamic Hazards will occur.
2. To make the 2-level realization of the function F = A’B + AC free from static-
1 logic hazard, Add a product term BC to F, and implement accordingly.
3. To avoid a static-0 logic hazard in a circuit, Avoid any product term
containing both a variable and its complement.
4. Essential Hazards is the effects of a single input variable change reaching
one feedback path before another feedback path.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

46. CONTENTS:
Design
Verilog Code
OUTCOMES:
Students will be able to design and write a code for vending machine.
MODULE-VI: Vending-Machine Controller
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ENGINEERING COLLEGE

47. Vending-Machine Controller
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ENGINEERING COLLEGE
Specification:
• It accepts nickels and dimes.
• A total of 15 cents is needed to release the candy from the machine.
• No change is given if 20 cents is deposited.

48. Flow table
P1 = (ADGJ)(BE)(C)(FIL)(HK)
P2 = (A)(D)(GJ)(B)(E)(C)(FIL)(HK)
P3 = P2
Vending-Machine Controller
MATRUSRI
ENGINEERING COLLEGE
State minimization
Merger diagram

49. Vending-Machine Controller
MATRUSRI
ENGINEERING COLLEGE
Reduced flow tables State diagram

50. Vending-Machine Controller
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ENGINEERING COLLEGE
Transition Diagram
Embedded on Cube
Excitation table based on the state
assignment

51. Vending-Machine Controller
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ENGINEERING COLLEGE
A
Y1 = ͞͞Ny2 + Ny1 + Dy1 + y1y3 + y1y2
Y2 = Ny͞1 + Ny2 + y͞1y3 + D͞ y2y͞3 + Dy2y3
Y3 = D ͞y1 + y2y3 + Ny1y2 + D ͞y3N ͞

52. Vending-Machine Controller
MATRUSRI
ENGINEERING COLLEGE
module vend(
coin, clock, reset, newspaper);
input [1:0] coin;
input clock,reset;
output newspaper;
wire [1:0] NEXT_STATE;
reg [1:0] PRES_STATE;
parameter s0 = 2'b00, s5 = 2'b01, s10 = 2'b10, s15 = 2'b11;
function [2:0] fsm;
input [1:0] fsm_coin;
input [1:0] fsm_PRES_STATE;
reg fsm_newspaper;
reg [1:0] fsm_NEXT_STATE;
begin

53. Vending-Machine Controller
MATRUSRI
ENGINEERING COLLEGE
case (fsm_PRES_STATE)
s0:
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s5;
end
else
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s0;
end
s5:
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
else
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s5;
end

54. Vending-Machine Controller
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ENGINEERING COLLEGE
s10:
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15;
end
else
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
S15: begin
fsm_newspaper = 1'b1;
fsm_NEXT_STATE = s0;
end
endcase
fsm = {fsm_newspaper, fsm_NEXT_STATE};
end
endfunction
assign {newspaper, NEXT_STATE} =
fsm(coin, PRES_STATE);
always @(posedge clock)
begin
if (reset == 1'b1)
PRES_STATE <= s0;
else
PRES_STATE <= NEXT_STATE;
end
endmodule

55. 1. By adding extra state variables, a race-free state assignment using log2n
state variables for a flow table that has n rows.
2. Increases the flexibility in state assignment by introducing an equivalent
new state for each existing state.
3. Unspecified entries in a flow table provide some flexibility in finding good
state assignments.
4. A good state assignment results if the transition diagram does not have any
diagonal paths.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

56. CONTENTS:
A Simple Arbiter
OUTCOMES:
Student will able to design and implement a FSM for serial adder
MODULE-VIII: Additional Topic
MATRUSRI
ENGINEERING COLLEGE

57. A Simple Arbiter
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ENGINEERING COLLEGE
When various devices need to use the resource, they have to request to do so.
These requests are handled by an arbiter circuit.
Arbitration structure
Handshake signaling
Communication between two entities in the asynchronous environment,
known as handshake signaling.

58. A Simple Arbiter
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ENGINEERING COLLEGE
State diagram ASM Chart

59. A Simple Arbiter
MATRUSRI
ENGINEERING COLLEGE
Modified State diagram
Flow Table
Excitation Table
Y1 = r2r1 + r1y2 Y2 = r2r1 + r2y2
g1 = y1 g2 = y2

60. A Simple Arbiter
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ENGINEERING COLLEGE
An alternative for avoiding a critical race
Flow Table
Excitation Table
Y1 = r1y2
Y2 = r1r2y1 + r2y2
g1 = y1
g2 = y2

61. A Simple Arbiter
MATRUSRI
ENGINEERING COLLEGE
Mealy model for the arbiter FSM
State diagram:
Flow Table:
Excitation Table:
Y = r2r1 + r1y + r2y
g1 = r1y
g2 = r2y

62. 1. When various devices need to use the resource, then requests are handled
by an arbiter circuit.
2. Each device communicates with the arbiter by means of two signals—
Request and Grant.
3. Communication between two entities in the asynchronous environment,
known as handshake signaling.
4. The time elapsed between the changes in the cause-effect signals depends
on the specific implementation of the circuit.
Questions & Answers
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ENGINEERING COLLEGE

63. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 Define ASM Block and explain with example. L2 CO4
2 Draw ASM chart for the arbiter FSM. L1 CO4
3 Explain transition and flow table in asynchronous
sequential circuit.
L2 CO4
4 List out the elements of ASM chart and their operation. L1 CO4
5 Draw ASM chart for vending machine. L1 CO4
6 Explain Hazards in combinational circuits with examples. L2 CO4
7 Differentiate between state table and flow table. L3 CO4
8 Draw ASM chart for given FSM model
shown below.
L1 CO4
9 Differentiate between ASM and ASMD chart. L3 CO4
10 Explain simplifications and timing considerations. L2 CO4
PS Input X
0 1
A
B
C
D
E
B/0 E/0
A/1 C/1
B/0 C/1
C/0 E/0
D/1 A/0

64. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 Design vending machine controller and implement its verilog
code.
L5 CO4
2 Analyze given asynchronous sequential circuit and obtain its
state table and timing diagram.
L5 CO4
3 Explain controller design with one hot design. L2 CO4
4 With neat ASM chart and Verilog code, explain Binary
multiplier.
L2 CO4
5 Describe steps involved in an analysis procedure of
asynchronous sequential circuits.
L5 CO4

65. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
6 Derive a flow table that describes the behaviour of the as
shown
L3 CO4
7 Analyze the given asynchronous sequential circuit. L5 CO4

66. Assignment Questions
MATRUSRI
ENGINEERING COLLEGE
1. Analyze given asynchronous sequential circuit and obtain its state table
and timing diagram.
2. With the help of block diagram, explain fundamental mode asynchronous
sequential machine.
3. Explain one hot state controller design.
4. Explain Binary multiplier with neat ASMD chart and write a verilog code.
5. Design vending machine controller. Draw its ASM chart and implement its
verilog code.