VLSI Design and Layout Practice Lect5 – Stick Diagram & Scalable Design Rules Danny Wen-Yaw Chung Institute of Electronic Engineering Chung-Yuan Christian University Sept. 2008
IC Layout Concept and Examples
I. Stick Diagram
II. Design Rules
III. Layout Verification
A. Basic Concept
1. Based on the view point of IC layout, the stick diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks.
Legend: contact metal 2 metal 1 poly ndiff pdiff VDD in VSS out ■
A. Basic Concept
2. Although the stick diagram is an abstract presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2-diomensional plane and reach the aim same as the physical layout does.
3. The stick diagram is similar to a backbone of the real layout but without the real size and aspect ratio of the devices , it still can reflect the real condition to layout of the silicon chip.
B. Notations of the stick diagram
between the transistor level and the mask (layout) level.
Gives topological information
(identifies different layers and their relationship)
Assumes that wires have no width.
It is possible
to translate stick diagram automatically to layout with correct design rules.
CMOS Inverter Mask Layout Min. spacing and line width consideration
Lambda design rules are based on a reference metric λ that has units of um.
All widths, spacing and distances are written in the form Value = m λ
Where m is scaling multiplier.
<e.g.> λ = 1um w = 2 λ =2um
s = 3 λ =3um
Lambda-based Design Rules
Lambda based design: half of technology since 1985. As technology changes with smaller dimensions, a simple change in the value of can be used to produce a new mask set. All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2 . Minimum metal to metal spacing = 3 Lambda-based Design Rules 6 2 6 3 3
Active Contact and Surround Rule
Potential Problem - Misalignment
Potential Problem – Short between Source and Drain
Degree of anisotropy A = 1 – r lat /r vert Where r respective etch rates Physical Limitations
Design Rule (0)
Due to the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment.
In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule 。
=> To check the min. line width and spacing based on the design rules.
C. ERC(Electrical Rule Check) ：
=> To check the short circuit between Power and Ground, or check the floating node or devices.
D. LVS(Layout versus Schematic) ：
=> To verify the consistency between Schematic and Layout. For example ： to check the amount of transistor numbers, sizes of W/L.
E. LPE or PEX(Layout Parameter Extraction) ：
=> From the database of layout, to extract the devices with parasitics including effective W/L, parasitic capacitances and series resistance. The extracted file is in SPICE format and can be used for Post-Layout Simulation 。
Layout Verification F. Simulations Pre-Layout Simulation - before layout work Post-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.