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The Microarchitecure Of FPGA Based Soft Processor

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Deepak Tomar

this presentation is on the Paper "The Microarchitecure Of FPGA Based Soft Processor" by Peter Yiannacouras, Jonathan Rose and J Gregory Steffan Dept. of Electrical and Computer Engineering University of Toronto

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The Microarchitecure of FPGA-Based Soft Processor Peter Yiannacouras, Jonathan Rose and J Gregory Steffan Dept. of Electrical and Computer Engineering University of Toronto Presented By: Deepak Tomar CS08M054,M Tech II Year CS & E Dept
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Aim ,[object Object],[object Object],[object Object]
The Basics First ,[object Object],[object Object],[object Object],[object Object]
Field Programmable Gate Array (FPGA) ,[object Object],[object Object],[object Object],[object Object]
How FPGAs work ? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],FLIP-FLOP LUT LOGIC CELL Logic Function as Text File Binary file post compilation of Text File Computer FPGA Cable
Soft Processor/ Hard Processor ,[object Object],[object Object],[object Object],Altera Excalibur Altera Nios Xilinx Virtex II Pro Xilinx Microblaze Developer Hard Processor Developer Soft Processor
Motivation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Understanding Soft Processor Microarchitecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Overview of the SPREE system SPREE RTL Generator Efficiently Synthesizable RTL RTL CAD Flow RTL Simulator ,[object Object],[object Object],[object Object],[object Object],[object Object],Embedded Benchmarks Applications Architecture Description
Preview of capabilities of SPREE Area (Equivalent LEs) 0 200 400 600 800 1000 1200 1400 1600 1800 12000 10000 8000 6000 4000 2000 0 Average Wall Clock Time ( µs ) Multiply Full Hardware Support Multiply Software Routine Altera NiosIIe Altera NiosIIs Altera NiosIIf
SPREE RTL Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SPREE RTL Generator Datapath Verification Datapath Instantiation Control Generation Component Library (Efficient RTL) SPREE RTL Generator Datapath Description ISA Description Efficient RTL Description
SPREE RTL Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Datapath Description as Interconnection of Components Shift Instruction Memory Reg File mux mux ALU Data Mem
SPREE RTL Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Sample component description for a simplified ALU ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],opcode Functionality Interface Port value Latency in cycles Bit width GENOPs : ADD,SUB and SLT inA inB ADD SUB SLT result
SPREE RTL Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
MIPS ADDI instruction shown as Data Dependence Graph IFETCH REGREAD SIGN_EXT ADD REGWRITE Rule: No GENOP can execute until all its inputs are ready
SPREE RTL Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SPREE RTL Generator Datapath Verification Datapath Instantiation Control Generation Component Library (Efficient RTL) SPREE RTL Generator Datapath Description ISA Description Efficient RTL Description
Generating a soft processor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Experimental Framework ,[object Object],[object Object],[object Object],[object Object],[object Object]
An Altera Stratix FPGA
Experimental Framework (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Exploring Soft Processor Microarchitecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Avg wall-clock-time vs area of NiosII and generated processor Area (Equivalent LEs) 0 200 400 600 800 1000 1200 1400 1600 1800 12000 10000 8000 6000 4000 2000 0 Average Wall Clock Time ( µs ) Multiply Full Hardware Support Multiply Software Routine Altera NiosIIe Altera NiosIIs Altera NiosIIf
Comparison with NiosII variations 135 1.97 NiosIIf 120 2.36 NiosIIs 9% smaller and 11% faster than NiosIIs 80 1.36 SPREE Generated Processor Comment Clock(MHz) CPI Processor
Avg wall-clock-time vs area of NiosII and generated processor Area (Equivalent LEs) 0 200 400 600 800 1000 1200 1400 1600 1800 12000 10000 8000 6000 4000 2000 0 Average Wall Clock Time ( µs ) Multiply Full Hardware Support Multiply Software Routine Altera NiosIIe Altera NiosIIs Altera NiosIIf
Comparison with NiosII variations 159 6 NiosIIe Within 15% of area and 11% faster than NiosIIe 82 2-3 SPREE Smallest Generated Processor Comment Clock(MHz) CPI Processor
Conclusion ,[object Object],[object Object],[object Object]
References ,[object Object],[object Object],[object Object]
THANK YOU
SPREE RTL Generator Datapath Verification Datapath Instantiation Control Generation Component Library (Efficient RTL) SPREE RTL Generator Datapath Description ISA Description Efficient RTL Description
NiosII variations ,[object Object],[object Object],[object Object]
Generator collects all timing information from each component Analyze datapath and infer pipeline stage of each component In each pipeline, local stall signals extracted and propagated (stall network) to earlier stages Enables generated if component is not stalled Generation of Enable Signals
[object Object],[object Object],[object Object]

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The Microarchitecure Of FPGA Based Soft Processor

  • 1. The Microarchitecure of FPGA-Based Soft Processor Peter Yiannacouras, Jonathan Rose and J Gregory Steffan Dept. of Electrical and Computer Engineering University of Toronto Presented By: Deepak Tomar CS08M054,M Tech II Year CS & E Dept
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  • 11. Preview of capabilities of SPREE Area (Equivalent LEs) 0 200 400 600 800 1000 1200 1400 1600 1800 12000 10000 8000 6000 4000 2000 0 Average Wall Clock Time ( µs ) Multiply Full Hardware Support Multiply Software Routine Altera NiosIIe Altera NiosIIs Altera NiosIIf
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  • 13. SPREE RTL Generator Datapath Verification Datapath Instantiation Control Generation Component Library (Efficient RTL) SPREE RTL Generator Datapath Description ISA Description Efficient RTL Description
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  • 15. Datapath Description as Interconnection of Components Shift Instruction Memory Reg File mux mux ALU Data Mem
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  • 19. MIPS ADDI instruction shown as Data Dependence Graph IFETCH REGREAD SIGN_EXT ADD REGWRITE Rule: No GENOP can execute until all its inputs are ready
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  • 21. SPREE RTL Generator Datapath Verification Datapath Instantiation Control Generation Component Library (Efficient RTL) SPREE RTL Generator Datapath Description ISA Description Efficient RTL Description
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  • 24. An Altera Stratix FPGA
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  • 27. Avg wall-clock-time vs area of NiosII and generated processor Area (Equivalent LEs) 0 200 400 600 800 1000 1200 1400 1600 1800 12000 10000 8000 6000 4000 2000 0 Average Wall Clock Time ( µs ) Multiply Full Hardware Support Multiply Software Routine Altera NiosIIe Altera NiosIIs Altera NiosIIf
  • 28. Comparison with NiosII variations 135 1.97 NiosIIf 120 2.36 NiosIIs 9% smaller and 11% faster than NiosIIs 80 1.36 SPREE Generated Processor Comment Clock(MHz) CPI Processor
  • 29. Avg wall-clock-time vs area of NiosII and generated processor Area (Equivalent LEs) 0 200 400 600 800 1000 1200 1400 1600 1800 12000 10000 8000 6000 4000 2000 0 Average Wall Clock Time ( µs ) Multiply Full Hardware Support Multiply Software Routine Altera NiosIIe Altera NiosIIs Altera NiosIIf
  • 30. Comparison with NiosII variations 159 6 NiosIIe Within 15% of area and 11% faster than NiosIIe 82 2-3 SPREE Smallest Generated Processor Comment Clock(MHz) CPI Processor
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  • 34. SPREE RTL Generator Datapath Verification Datapath Instantiation Control Generation Component Library (Efficient RTL) SPREE RTL Generator Datapath Description ISA Description Efficient RTL Description
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  • 36. Generator collects all timing information from each component Analyze datapath and infer pipeline stage of each component In each pipeline, local stall signals extracted and propagated (stall network) to earlier stages Enables generated if component is not stalled Generation of Enable Signals
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