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FPGA Introduction


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field programmable gate array

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FPGA Introduction

  1. 1. FPGA By :- Kamlesh Kumar
  2. 2. WHAT IS A FPGA? Field Programmable Gate Array (FPGA)
  3. 3. Programmability Three programming methods:- 1. SRAM –Based (Xilinx, Altera) 2. Antifuse Technology (Actel, Quicklogic) 3. EPROM/EEPROM
  4. 4.  FPGAs allow designers to change their designs very late in the design cycle– even after the end product has been manufactured and deployed in the field. In addition, Xilinx FPGAs allow for field upgrades to be completed remotely, eliminating the costs associated with re-designing or manually updating electronic systems
  5. 5. FPGA Block Structure
  6. 6.  Configurable Logic Blocks (CLBs)  Interconnect  Select I/O (IOBs)  Memory  Complete Clock Management Common FPGA Features
  7. 7.  Primary resources for design Combinational functions Flip flops  CLB contains two slice  Connected to switch matrix for routing to other FPGA resources  Carry chain runs in vertically in a column from one slice to the one above Configurable Logic Blocks (CLBs)
  8. 8.  Two type of slices SLICEM:- Full Slice  LUT can be used for logic and memory/SRL  Has wide MUX and carry chain SLICEL:- logic and arithmetic slice  LUT can only be used for logic(Not memory)  Has wide MUX and carry chain
  9. 9.  FPGA Slice Resource  Four six-input look-up table  Wide MUX  Carry chain  Four Flip-flop/latches  Four addition Flip-flops
  10. 10. Basic Configurable Logic Block Structure
  11. 11.  The design software makes the interconnect routing task hidden to the user unless specified otherwise, thus significantly reducing design complexity.  XADC  AMS Interconnect
  12. 12.  I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards Select I/O (IOBs)
  13. 13. Basic Select I/O (IOBs) Structure
  14. 14.  Block RAM/FIFO  Fully Synchronous operation  Optional internal pipeline register for higher frequency operation.  Two independent port access common data Individual address, clock, write enable , clock enable  Multiple configuration option True dual-port, Simple dual-port, Single port Memory
  15. 15.  Global Clock Buffer(BUFG)  Vertical spins  Global clock network  BUFIO  i/o clock network Complete Clock Management
  16. 16. Xilinx FPGAs
  17. 17. By Market By Technology Aerospace and Defense Industrial Audio Automotive Medical Security Broadcast Wireless Communications Video and Imaging Consumer Electronics Wired Communications High Performance Computing FPGA Applications