“Fast-track Design Cycles Using Lattice’s FPGAs,” a Presentation from Lattice Semiconductor
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For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2023/06/fast-track-design-cycles-using-lattices-fpgas-a-presentation-from-lattice-semiconductor/ Hussein Osman, Segment Marketing Director at Lattice Semiconductor, presents the “Fast-track Design Cycles Using Lattice’s FPGAs” tutorial at the May 2023 Embedded Vision Summit. Being first to market can mean the difference between success and failure of a new product. But rapid product development brings challenges. With the growing use of AI in embedded vision applications, designers need more flexibility to change and refine their designs during development and over the product life cycle. The choice of processor type has a significant impact on development time. In the past, designers often opted for ASICs, but their development cost and inflexibility makes them less suitable for today’s rapidly evolving requirements. In contrast, FPGAs can be reprogrammed after deployment. Additionally, FPGAs’ parallel processing capabilities make them valuable for offloading tasks from a CPU, adding processing power and freeing the CPU for other tasks. In this talk, Osman shows how Lattice’s Avant family, a new class of midrange FPGAs, coupled with the sensAI solution stack, brings optimized AI performance and high-speed connectivity to help designers accelerate design cycles, adapt designs as they go and accommodate changing algorithms without sacrificing power consumption and size.
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“Fast-track Design Cycles Using Lattice’s FPGAs,” a Presentation from Lattice Semiconductor
- 1. Fast-Track Design Cycles Using Lattice’s FPGAs Hussein Osman Marketing Director Lattice Semiconductor
- 2. Embedded Vision Trends Support multiple sensors and displays Move to higher resolutions and faster frame rates Connect MIPI and legacy components Enable AI processing at low power These trends require hardware with: Low Power Small Form Factor High Performance High Reliability Ease of Use 2 Lattice Semiconductor (NASDAQ: LSCC)
- 3. FPGA adaptable architecture is required to accelerate compute efficiently Edge devices typically run on battery and are thermally challenged requiring low power profile GPUs used as accelerators best when executing the same instruction in parallel, also power hungry Rapidly changing deep learning AI algorithms Heterogenous compute is required with HW accelerators assisting CPUs Getting to market quickly Compute requirement doubling every 3 month, 7x faster than Moore’s law SoC based heterogeneous compute is rigid, the HW accelerators are not programable Spinning new versions of ASICs and ASSPs is costly limiting the update cycle of the HW blocks Edge Processing Challenges 3 Lattice Semiconductor (NASDAQ: LSCC)
- 4. Scalable Performance To Handle Multiple Use Case Executes multiple use cases in parallel or serial Secure Secure device configuration Hardware Programmable Adapts to fast changing machine learning algorithms Ultra-low Power 1 milliwatt to 5 W power consumption Flexible Computation Resources Pre and post processing of data such as ISP, FFT and filtering Why FPGA for Edge AI 4 Lattice Semiconductor (NASDAQ: LSCC)
- 5. Hardware optimization Algorithm optimization Continuous improvement and new use cases = & AI models are rapidly evolving 80 70 60 50 2012 2021 AI classification model innovation The Speed of AI Innovation Benefits Programmable Logic to Keep Delivering the Best Experience. 5 Lattice Semiconductor (NASDAQ: LSCC)
- 6. FPGA Architecture – Programable Distributed Resources Building blocks are distributed throughout the fabric Extensive interconnect routing connecting blocks Flexible I/Os to move data in and out Similar approach to modern AI ASICs 6 Lattice Semiconductor (NASDAQ: LSCC)
- 7. AI Models Evolve Rapidly, Requiring Agile Development Cycles that ASICs Cannot Match FPGA 2 Design 1 Design 2 Design 3 Design 4 ASIC Gen 2 Market leadership FPGA 1 Design 1 Design 2 Design 3 Design 4 Fast iterations to improve experience Introduction of new experiences ASIC Gen 1 7 Lattice Semiconductor (NASDAQ: LSCC)
- 8. Vision Pipeline: End-to-end Hardware Implementation Sensing and conditioning DSP, ISP, downscaling, rotation, gamma correction Intelligent processing AI accelerator Understanding the results Post processing, filtering, overlay, upscaling 8 Lattice Semiconductor (NASDAQ: LSCC)
- 9. Smart Home Smart Car Smart City Smart Factory Hand Gesture Detection Key Phrase Detection Object Counting Neural Network Accelerators CNN Compact Accelerator CNN Co-Processor Accelerator CNN Accelerator Upduino ECP5™ EVDK iCE40™ UltraPlus 1-20 mW, 5.5 mm2 ECP5™ 250 - 850 mW, 100 mm2 CrossLink™-NX Voice and Vision ML Board CrossLink™-NX 50-200 mW, 16 mm2 CertusPro™-NX 400 mW, 81 mm2 CertusPro™-NX Voice and Vision ML Board CNN Plus Accelerator sensAI Studio Object Classification Human Attention Tracking Human Presence Detection Client Compute Experiences Neural Network Compiler Avant Evaluation Board Avant™ 1 - 5 W, 100 mm2 Advanced CNN Accelerator CUSTOM DESIGN SERVICES REFERENCE DESIGNS / DEMOS SOFTWARE TOOLS IP CORES HARDWARE PLATFORMS 9 GENERAL NOTICE: Other entity and product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
- 10. Applications Supported Across FPGAs 10 Lattice Semiconductor (NASDAQ: LSCC) Performance Vibration detection Object detection Key phrase detection Multiple objects detection Multiple camera stream analytics Multiple objects tracking Non- biometric object identification Biometric identification Scene segmentation iCE40 UltraPlus CrossLink-NX CertusPro-NX Single camera stream analytics Avant Throughput
- 11. 5X Higher Capacity TM 10X More Bandwidth 30X Faster Performance 11 Note: Comparing Lattice Nexus and Lattice Avant platforms. Advancement in Mid Range FPGAs Lattice Semiconductor (NASDAQ: LSCC)
- 12. OPTIMIZED COMPUTE Enhanced DSP tuned for AI inferencing Flexible and distributed embedded memory On-Chip Compute Elements Programmable fabric architected for low power Power optimized embedded memory and DSP Power efficient SERDES and I/O designs Built-in protocol logic for lower system power POWER EFFICIENCY ADVANCED CONNECTIVITY Configurable 25G SERDES Dedicated PCIe ® Gen 4 x8 controllers Programmable high performance I/O High speed memory interfaces up to DDR5 12 Lattice Semiconductor (NASDAQ: LSCC)
- 13. Hardware Optimized Design Methodology Trained model Quantized weights and instructions FPGA bitstream NN models NN IP System interface Training dataset Training scripts NN compiler Training FPGA Design Lattice sensAI components Lattice FPGA design tools ML frameworks 13 Lattice Semiconductor (NASDAQ: LSCC)
- 14. Software Optimized Design Methodology 14 Lattice Semiconductor (NASDAQ: LSCC)
- 15. Lattice sensAI Studio 15 Lattice Semiconductor (NASDAQ: LSCC)
- 16. Example FPGA Implementation for Computer Vision 16 Lattice Semiconductor (NASDAQ: LSCC)
- 17. Object Classification – Real Time Video Analysis Features Video input 1080P Inferencing speed 77 FPS (17x CertusPro-NX) Power 1.6 W (4x CertusPro-NX) Processing resolution 480 x 288 NN model Mobilenet v2 System Block Diagram 17 Lattice Semiconductor (NASDAQ: LSCC) FPGA Engine # of DSP Engines # of INT8 Multipliers FPGA Resources Usage FPS Avant 500 Advanced CNN 272 1088 15% 77 CertusPro-NX Advanced CNN 72 144 32% 10 CrossLink-NX CNNPlus 18 36 46% 5 Video Player Display Avant Evaluation Board HDMI HDMI Crop Down Scale CNN Engine Post Processing and Overlay Video lnput Video Output HDMI Port Processor (RX) HDMI Parallel HDMI Port Processor (TX)
- 18. Creating Ready for Production Solutions Advanced AI Technology for the Edge Presence Detection Depth Sensing 3D Head & Gesture Tracking Face ID & Landmarks Tracking Eye Feature Detection & Tracking Human Skeleton Detection Object Detection CLIENT AUTOMOTIVE INDUSTRIAL TM 18 Lattice Semiconductor (NASDAQ: LSCC)
- 19. Essential Features Wake on Approach Attention Tracking 19 Lattice Semiconductor (NASDAQ: LSCC)
- 20. Privacy & Security 20 Lattice Semiconductor (NASDAQ: LSCC)
- 22. Summary and Takeaways Edge AI challenges require adaptable architecture for continued innovation FPGAs’ programmability allows tinkering with the end-to-end designs before and after production A hardware-programable AI accelerator allows systems to evolve with new AI models Vision applications need flexible acceleration for the entire pipeline New class of mid range FPGAs come with DSP, memory and I/O advancement Tools, IPs and examples designs accelerate time to market Production-ready solutions can be customized and embedded into different applications Lattice Semiconductor (NASDAQ: LSCC) 22
- 23. Demos and Additional Resources