The SAI interface (Serial Audio Interface) is a peripheral that communicates with external audio devices, supporting a wide set of audio protocols: PDM Interface (Pulse Density Modulation) I2S Philips standards, (Inter-IC Sound) SPDIF Output, (Sony/Philips Digital InterFace) PCM, (Pulse Code Modulation) TDM, (Time Division Multiplexing) AC’97, (Audio Codec ’97 from Intel)

1. By/ Mostafa Khamis
Mostafaa.soc@riotmicro.com
SAI Design and Verification
Specs

2.  Introduction
 Block architecture
 Free protocol modes
 SPDIF protocol
 PDM interface
 AC’97 protocol
 Low-power modes
 Verification Specs.
Outline
Mostafa KhamisSAI Design and Verification Specs

3. Introduction

4.  The SAI interface (Serial Audio Interface) is a peripheral that communicates with
external audio devices, supporting a wide set of audio protocols:
 PDM Interface (Pulse Density Modulation)
 I2S Philips standards, (Inter-IC Sound)
 SPDIF Output, (Sony/Philips Digital InterFace)
 PCM, (Pulse Code Modulation)
 TDM, (Time Division Multiplexing)
 AC’97, (Audio Codec ’97 from Intel)

 Fully Configurable
 Two independent sub-blocks.
Overview
Mostafa KhamisSAI Design and Verification Specs

5.  Audio sampling rates: 44.1, 16, 48, 96, and 192 Khz
 Master or slave mode for each sub-block

 Data input, output, or full-duplex for each sub-block.

 Clock generator for each sub-block

 Synchronization between sub-blocks or with other SAIs

 Companding modes (Micro-Law, A-Law)

 8-word FIFO size.

 2 DMA interfaces.

 2 Interrupt lines.

 Stereo/Mono audio frame capability.
SAI Features
Mostafa KhamisSAI Design and Verification Specs

6. Block Architecture

7. SAI embeds:

 Two independent sub-blocks (channels):
 Each sub-block can be configured in Receiver or Transmitter
 mode and in Master or Slave mode with its own protocol.

 A clk generator
 A flexible serial interface
 FIFO buffers
 APB interface
 DMA and interrupt services


 Synchronization mechanism
 Internal and external synchronization allows
 two sub-blocks to be synchronized, or several
 SAI interfaces to be synchronized.
Block Diagram
Mostafa KhamisSAI Design and Verification Specs

8. SAI embeds:

 IO line management
 Each sub-block can handle up to four IOs

 A PDM interface
 allows the connection of up to 8
 digital microphones.

Block Diagram
Mostafa KhamisSAI Design and Verification Specs

9.  Rich Kernel clock selection (SAI_CK_X):
 The kernel clock is used to generate the timing
of the SAI when in Master mode.
 One of the 3PLL outputs (which are
 embedded in STM32H7), or
 One of the oscillator outputs, or
 Clock from pad

 Flexible internal synchronization
 Each SAI can provide a synchronization to
 the 3 other SAI (to support multi-lane devices)
 Each SAI can be synchronized with one of
 the 3other SAIs.

 Possibility to support both 48 KHz and 44.1 Khz
 streams simultaneously in parallel

 Note: SAI4 has two independent multiplexers for the
 kernel clock selection because it is located in the D3 domain.
SAI in the circuit
Mostafa KhamisSAI Design and Verification Specs

10. Master Full-Duplex or Dual Lane
Mostafa KhamisSAI Design and Verification Specs

11. Slave Full-Duplex or Dual Lane
Mostafa KhamisSAI Design and Verification Specs

12. Free Protocol Modes

13.  The free protocol modes should be selected to configure SAI:
 I2S Philips standard
 I2S MSB or LSB-justified
 TDM or PCM
 Data Justification (LSB/MSB first)
 Data Size, Slot (channel) size
 Number of slots per frame
 Data position into a slot
 Sampling edge of the serial clock

 The free protocol mode is used to adjust the following:
 Frame size, frame polarity, frame period
 Frame active level size
 Frame synchronization mode
 Master/Slave mode
 Single or multiple or full-duplex data lanes
Protocol Modes
Mostafa KhamisSAI Design and Verification Specs

14. 
I2S-like Protocol Timings
Mostafa KhamisSAI Design and Verification Specs

15. 
TDM-like Protocol Timings
Mostafa KhamisSAI Design and Verification Specs

16.  Up to 16 slots per audio frame

 Each slot can be defined as active or not

 Possibility to adjust the position of the data within a slot
 by defining the first bit offset FBOFF

 Possibility to set the data line in HiZ
 For inactive slots
 During FBOFF (First bit offset) area which is used
 to control the position of the data inside each slot
Slot Timings
Mostafa KhamisSAI Design and Verification Specs

17. Free Protocol Modes
Mostafa KhamisSAI Design and Verification Specs

18. SAI Synchronization
Mostafa KhamisSAI Design and Verification Specs

19. Companding
Mostafa KhamisSAI Design and Verification Specs

20. Specific Feature: Mute Mode
Mostafa KhamisSAI Design and Verification Specs

21. Anticipated/Late Frame Error
Mostafa KhamisSAI Design and Verification Specs

22. SPDIF Protocol

23. SPDIF Protocol
Mostafa KhamisSAI Design and Verification Specs

24. SPDIF Protocol
Mostafa KhamisSAI Design and Verification Specs

25. SPDIF Protocol
Mostafa KhamisSAI Design and Verification Specs

26. SPDIF Protocol
Mostafa KhamisSAI Design and Verification Specs

27. PDM Protocol

28. PDM Interface
Mostafa KhamisSAI Design and Verification Specs

29. AC’97 Protocol

30. AC’97 Protocol
Mostafa KhamisSAI Design and Verification Specs

31. Low Power Modes

32. Low-power Modes
Mostafa KhamisSAI Design and Verification Specs

33. Verification Specs

34. UVM Environment
Mostafa KhamisSAI Design and Verification Specs

35. Mostafa KhamisSAI Design and Verification Specs