This presentation provides a focused but comprehensive discussion on potential reliability issues that can arise within Pb-free processes. Areas of potential high risk are examined. For each reliability concern, a brief description is provided, followed by the current state of industry knowledge and an opportunity for risk mitigation based upon the product design, materials, complexity, volumes, and customer expectations of reliability. A final summary provides the attendees a roadmap for ensuring the reliability of Pb-free product.

1. Solving Problems with Reliability in the Lead-Free Era
SMTA ICSR
Toronto, Canada
May 7, 2011
Cheryl Tulkoff, ASQ CRE DfR Solutions Sr. Member of the Technical Staff

2. High Reliability Course Abstract
oThis webinar provides a focused but comprehensive discussion on potential reliability issues that can arise within Pb-free processes. Areas of potential high risk are examined. For each reliability concern, a brief description is provided, followed by the current state of industry knowledge and an opportunity for risk mitigation based upon the product design, materials, complexity, volumes, and customer expectations of reliability. A final summary provides the attendees a roadmap for ensuring the reliability of Pb-free product.

3. Instructor Biography
oCheryl Tulkoff has over 17 years of experience in electronics manufacturing with an emphasis on failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle beginning with semiconductor fabrication processes, into printed circuit board fabrication and assembly, through functional and reliability testing, and culminating in the analysis and evaluation of field returns. She has also managed no clean and RoHS-compliant conversion programs and has developed and managed comprehensive reliability programs.
oCheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a published author, experienced public speaker and trainer and a Senior member of both ASQ and IEEE. She holds leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer.
oShe has a strong passion for pre-college STEM (Science, Technology, Engineering, and Math) outreach and volunteers with several organizations that specialize in encouraging pre-college students to pursue careers in these fields.

4. Agenda
oQuick Refresher:
oSAC background & alternative alloys
oWhy did SAC305 become the standard LF alloy?
oPart I: The Current State of Lead Free
oComponents
oSuppliers
oConcerns
oRobustness
oTemperature Sensitivity
oMoisture Sensitivity
oDrivers
oComponents of specific interest
oPCBs
oSurface Finishes: Focus on Pb-free HASL
oLaminate Cracking & Delamination
oPTH Barrel Cracking & CAF (Conductive Anodic Filament)
oPad Cratering
oElectro-Chemical Migration (ECM)
oSolders
oDiscussion of 2nd gen alloys
oIntermetallic formation
oCopper Dissolution
oMixed Assembly
oWave and Rework
oLF Solder Fountain
oHole Fill Challenges
oPart II: Reliability Results
oShock/Drop Test Results
oSAC vs SnPb
oResults of alternative alloys
oVibration Results
oThermal Cycling
oSAC vs SnPb
oResults of alternative alloys
oWill there be one winner?
oFatigue (Shock & Vibration)
oMicrostructural Stability
oHALT/HASS
oConclusions

5. Quick Refresher
oWhy did SAC305 become the standard LF alloy?
oReadily available
oReasonable melting temp
oHad the least reliability issues compared to other options
SAC was never considered an ideal replacement for eutectic SnPb, it was simply the best choice at the time

6. Sn
Bi
Ag
Zn
Acceptable wetting
And high strength
High Melting Point 217C
Strength
Weakness
Melting point is almost the same as SnPb
Easily oxidizes, corro-
sion cracking, voids,
poor wetting
Mixing with Pb degrades strength and fatigue resistance
(silver)
(bismuth)
(zinc)
(tin)
Good wetting and
high strength
In
Inadequate source
of supply & corrosion
(indium)
+ Cu
SnAgCu became the industry accepted Pb- free alloy
Lead-free Alloy Summary

7. Module 1: Components Component Robustness

8. 8
Robustness - Components
Concerns
Potential for latent defects after exposure to Pb-free reflow temperatures
215°C - 220°C peak → 240°C - 260°C peak
Drivers
Initial observations of deformed or damaged components
Failure of component manufacturers to update specifications
Components of particular interest
Aluminum electrolytic capacitors
Ceramic chip capacitors
Surface mount connectors
Specialty components (RF, optoelectronic, etc.)

9. 9
Component Robustness: Electrolytic Capacitors
V-Chip is an adaptation of electrolytic capacitors to surface mount technology specifically designed to handle the high temperatures. Can they withstand the higher temperatures associated with Pb-free reflow?
Thru-hole electrolytic capacitors are not suitable for SMT and are not designed to handle reflow temperatures

10. 10
Electrolytic Capacitors (cont.)
Surface mount electrolytic capacitors (V-chip package)
Liquid electrolyte exposed to reflow and rework temperatures
Driven by a change in environments
Increase reflow/rework temperatures
Can result in case distortion and loss of seal
When does this mechanism occur?
How to differentiate this mechanism from other degradation behavior?
NIC
DfR
B. Willis, SMART Group

11. 11
Pb-Free Reflow Compatibility
0
100
200
300
400
500
600
700
800
1 10 100 1000 10000
Volume (mm3)
Time to Deformation (seconds)
0
100
200
300
400
500
600
700
800
1 10 100 1000 10000
Volume (mm3)
Time to deformation (seconds)
235°C 260°C
 At 235°C: 1 „failure‟ before peak temperature; 2 failures before 45 seconds
 At 260°C: 1 failure after 5 seconds at peak; 7 failures before 45 seconds
 Greatest risk
 Small (10-100 mm3 volume) and large (>1000 mm3) components

12. 12
V-Chip Capacitors: Reflow Profiling
oTemperature profiling during SnPb Reflow
oLarge ball grid array (BGA)
o16x18 V-chip (3600 mm3)
oPeak temperature of large can V-chip approximately 25°C to 30°C colder than BGA
oInterior solder joint under a BGA is often the coolest location on |the assembly
oThe BGA solder joint must reach 240-245ºC for Pb-free reflow
oSuggests V-chip housing will likely see a worst-case temperature of 210-220ºC
PCB: 16" x 17", 18 layer (100 mil)

13. V-Chip and Peak Reflow
oSome capacitor manufacturers have differentiated peak temperature based on case size for V-chip capacitors
oLarger capacitors can withstand higher peak temperatures
oPanasonic
o8mm to 10mm diameter: +240°C to +250°C
o12.5mm and larger diameter: +245°C to +255°C
www.arrowne.com/innov/in188/f_943.shtml (Panasonic)

14. 14
Long-Term Reliability
oAccelerated life testing after exposure to various Pb-free reflow conditions
o235ºC / 30 seconds
o245ºC / 30 seconds
o260ºC / 30 seconds
oReflow profile had no effect on lifetime
oIndication of low risk of latent defects
oOne deformed capacitor even showed nominal life
0.1110100100010000051015202530354045Time under Test at 165C (days) Normalized ESR Small (4 x 5) Medium (6.3 x 8) Large (12.5 x 14)

15. Electrolytic Capacitors: Summary
oPrimary electrolytic capacitor failure mode during Pb-free transition?
oOverheating during rework of microprocessor
oDrivers
oElectrolytic capacitors adjacent to the microprocessor
oThrough-hole electrolytic capacitors have lower boiling point than surface-mount electrolytic capacitors
oPoorly controlled rework conditions (rework temps can reach 300C for over 5 seconds)
oExample of off-line processes being a critical source of failures

16. 16
Ceramic Capacitors (Thermal Shock Cracks)
Due to excessive change in temperature
Reflow, cleaning, wave solder, rework
Inability of capacitor to relieve stresses during transient conditions.
Maximum tensile stress occurs near end of termination
Determined through transient thermal analyses
Model results validated through sectioning of ceramic capacitors exposed to thermal shock conditions
Three manifestations
Visually detectable (rare)
Electrically detectable
Microcrack (worst-case)
NAMICS
AVX

17. 17
Thermal Shock Crack: Visually Detectable
AVX

18. 18
Thermal Shock Crack: Micro Crack
Variations in voltage or temperature will drive crack propagation
Induces a different failure mode
Increase in electrical resistance or decrease capacitance
DfR

19. 19
Corrective Actions: Manufacturing
Solder reflow
Room temperature to preheat (max 2-3oC/sec)
Preheat to at least 150oC
Preheat to maximum temperature (max 4-5oC/sec)
Cooling (max 2-3oC/sec)
In conflict with profile from J-STD-020C (6oC/sec)
Make sure assembly is less than 60oC before cleaning
Wave soldering
Maintain belt speeds to a maximum of 1.2 to 1.5 meters/minute
Touch up
Eliminate

20. 20
Corrective Actions: Design
Orient terminations parallel to wave solder
Avoid certain dimensions and materials (wave soldering)
Maximum case size for SnPb: 1210
Maximum case size for SAC305: 0805
Maximum thickness: 1.2 mm
C0G, X7R preferred
Adequate spacing from hand soldering operations
Use manufacturer‟s recommended bond pad dimensions or smaller (wave soldering)
Smaller bond pads reduce rate of thermal transfer

21. 21
Is This a Thermal Shock Crack? No!
Cracking parallel to the electrodes is due to stack-up or sintering processes during capacitor manufacturing
These defects can not be detected using in-circuit (ICT) or functional test
Requires scanning acoustic microscopy (SAM)
With poor adhesion, maximum stress shifts away from the termination to the defect site
No correlation between failure rate and cooling rates (0.5 to 15ºC/sec)

22. 22
Flex Cracking of Ceramic Capacitors
Excessive flexure of PCB under ceramic chip capacitor can induce cracking at the terminations

23. 23
Flex Cracking of Ceramic Capacitors (cont.)
Excessive flexure of PCB under ceramic chip capacitor can induce cracking at the terminations
Pb-free more resistant to flex cracking
Correlates with Kemet results (CARTS 2005)
Rationale
Smaller solder joints
Residual compressive stresses
Influence of bond pad
Action Items
None
SnPb
SnAgCu

24. Summary
oRisk areas
oSmall volume V-chip electrolytic capacitors
oThrough hole electrolyic capacitors near large BGAs
oCeramic capacitors wave soldered or touched up
oActions
oSpec and confirm
oPeak reflow temperature requirements for SMT electrolytics (consider elimination if volume < 100mm3)
oTime at 300°C for through-hole electrolytics
oInitiate visual inspection of all SMT electrolytic capacitors (no risk of latency if no bulging or other damage observed)
oBan touch up of ceramic capacitors (rework OK)

25. Module 2: Components Temperature Sensitivity Moisture Sensitivity

26. Peak Temperature Ratings
oAka, „Temperature Sensitivity Level‟ (TSL)
oSome component manufacturers are not certifying their components to a peak temperature of 260ºC
o260ºC is industry default for „worst-case‟ peak Pb-free reflow temperature
oWhy lower than 260ºC?
oIndustry specification
oTechnology/Packaging limitation
26

27. Industry Specification (J-STD-020)
o Package size
o Number of component
manufacturers rely on table
and reflow profile suggested
in J-STD-020C
o Larger package size,
lower peak temperature
o Issues as to specifying dwell time
o J-STD-020C: Within 5ºC of 260ºC for 20-40 seconds
o Manufacturers: At 260ºC for 5-10 seconds
27

28. J-STD-020D.1 Reflow Profile (Update)
o Specification of peak package body temperature (Tp)
o Users must not exceed Tp
o Suppliers must be equal
to or exceed Tp
o Not yet widely adopted
28

29. TSL + MSL Example
o Peak temperature rating is 245C
o Problem, right?
o Not exactly
o Thickness > 2.5mm, Volume > 350mm3
o Peak temp specified by J-STD-020 is 245C
o Higher reflow temperature possible
o May require DOE / increase in MSL
29

30. TSL + MSL (cont.)
oIntel intends to comply with J-Std-020 MSL requirements, which establishes the peak temperature rating and MSL by package size
http://www.intel.com/technology/silicon/leadfree.htm
30

31. TSL + MSL (example – cont.)
oNEC has two soldering conditions
oIR50: 250C peak temperature
oIR60: 260C peak temperature
oFour packages (not parts) identified as IR50
o208pinQFP(FP): 28 x 28 x 3.2
o240pinQFP(FP): 32 x 32 x 3.2
o304pinQFP(FP): 40 x 40 x 3.7
o449pinPBGA: 27 x 27 x 1.7
oPeak temperatures could be 245C and still meet J-STD-020 requirements
oSuggests characterization separate from J-STD-020 may have been performed
31

32. 32
TSL (cont.)
Limited examples of technology and package limitations
Surface mount connectors (primarily overcome)
RF devices (already sensitive to SnPb reflow)
Opto-electronic (LEDs, opto- isolators, etc.)
Examples
Amphenol: “Amphenol connectors containing LEDs must NOT be processed using Lead-free infra-red reflow soldering using JEDEC-020C (or similar) profiles”
Micron / Aptina: “Some Pb-free CMOS imaging products are limited to 235°C MAX peak temperature”
http://www.amphenolcanada.com/ProductSearch/GeneralInfo/Disclaimer%20for%20Connectors%20containing%20LEDs.htm
B. Willis, SMART Group
http://download.micron.com/pdf/technotes/tn_00_15.pdf

33. Moisture Sensitivity Level (MSL)
oPopcorning controlled through moisture sensitivity levels (MSL)
oDefined by IPC/JEDEC documents J-STD-020D.1 and J-STD-033B
oHigher profile in the industry due to transition to Pb-free and more aggressive packaging
oHigher die/package ratios
oMultiple die (i.e., stacked die)
oLarger components
33

34. MSL: Typical Issues and Action Items
oIdentify your maximum MSL
oDriven by contract manufacturer (CM) capability and OEM risk aversion
oMajority limit between MSL3 and MSL4 (survey of the MSD Council of SMTA, 2004)
oHigh volume, low mix: tends towards MSL4 Low volume, high mix: tends towards MSL3
oNot all datasheets list MSL
oCan be buried in reference or quality documents
oEnsure that listed MSL conforms to latest version of J- STD-020
Cogiscan
34

35. MSL Issues and Actions (cont.)
oMost „standard‟ components have a maximum MSL 3
oComponents with MSL 4 and higher
oLarge ball grid array (BGA) packages
oEncapsulated magnetic components (chokes, transformers, etc.)
oOptical components (transmitters, transceivers, sensors, etc.)
oModules (DC-DC converters, GPS, etc.)
oMSL classification scheme in J-STD-020D is only relevant to SMT packages with integrated circuits
oDoes not cover passives (IPC-9503) or wave soldering (JESD22A111)
oIf not defined by component manufacturer, requires additional characterization
35

36. Aluminum and Tantalum Polymer Capacitors
Aluminum Polymer Capacitor 
Tantalum Polymer Capacitor 
36

37. Popcorning in Tantalum/Polymer Capacitors
oPb-free reflow is hotter
oIncreased susceptibility to popcorning
oTantalum/polymer capacitors are the primary risk
oApproach to labeling can be inconsistent
oAluminum Polymer are rated MSL 3 (SnPb)
oTantalum Polymer are stored in moisture proof bags (no MSL rating)
oApproach to Tantalum is inconsistent (some packaged with dessicant; some not)
oMaterial issues
oAluminum Polymer are rated MSL 3 for eutectic (could be higher for Pb-free)
oSensitive conductive-polymer technology may prevent extensive changes
oSolutions
oConfirm Pb-free MSL on incoming plastic encapsulated capacitors (PECs)
oMore rigorous inspection of PECs during initial build
37

38. Summary: Module 2
oKnow when peak temperature indicates true temperature sensitivity
oComponent manufacturer‟s peak temperature ratings deviate from J-STD-020
oPeak temperature ratings are very specific or nuanced in some fashion
oAsk component manufacturer for data confirming issues at temperatures below 260C
oConsider requiring MSL on the BOM for certain component packaging and technologies
oFocus on polymeric and large tantalum capacitors

39. Module 3: Printed Circuit Boards – Surface Finishes Pb-Free Hot Air Solder Level (HASL)

40. Solderability Plating: Pb-Free HASL
oIncreasing Pb-free solderability plating of choice
oPrimary material is Ni-modified SnCu (SN100CL)
oInitial installations of SAC being replaced
oOnly Vicor recently identified as using SAC HASL (Electronic Design, Nov 2007)
oCo-modified SnCu also being offered (claim of 80 installations [Metallic Resources])
oSelection driven by
oStorage
oReliability
oSolderability
oPlanarity
oCopper Dissolution

41. Pb-Free HASL: Ni-modified SnCu
oPatented by Nihon Superior in March 1998
oClaimed: Sn / 0.1-2.0% Cu / 0.002-1% Ni / 0-1% Ge
oActual: Sn / 0.7% Cu / 0.05% Ni / 0.006% Ge
oRole of constituents
oCu creates a eutectic alloy with lower melt temp (227C vs. 232C), forms intermetallics for strength, and reduces copper dissolution
oNi suppresses formation of b-Sn dendrites, controls intermetallic growth, grain refiner
oGe prevents oxide formation (dross inhibitor), grain refiner
Note: Current debate if Sn0.9Cu or Sn0.7Cu is eutectic

42. Pb-free HASL: Storage
oPCBs with SnPb HASL have storage times of 1 to 4 years
oDriven by intermetallic growth and oxide formation
oSN100CL demonstrates similar behavior
oIntermetallic growth is suppressed through Ni-addition
oOxide formation process is dominated by Sn element (similar to SnPb)
oLimited storage times for alternative Pb-free platings (OSP, Immersion Tin, Immersion Silver)

43. Pb-Free HASL: Intermetallic Growth
HASL and Flow: A Lead-Free Alternative, T. Lentz, et. al., Circuitree, Feb 2008, http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000243033
SN100C (150C for 1000 hrs)
SnPb (150C for 1000 hrs)
oSimilar intermetallic thickness as SnPb after long-term aging and multiple reflows

44. Pb-Free HASL: Reliability
oContract manufacturers (CMs) and OEMs have reported issues with electrochemistry-based solderability platings
oENIG: Black Pad, Solder Embrittlement
oImAg: Sulfur Corrosion, Microvoiding
oSome OEMs have moved to OSP and Pb-free HASL due to their „simpler‟ processes

45. Pb-Free HASL: Solderability
o Industry adage: Nothing solders like solder
http://www.daleba.co.uk/download%20section%20-%20lead%20free.pdf
HASL and Flow: A Lead-Free Alternative, T. Lentz, et. al., Circuitree, Feb 2008,
http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000243033
 Discussions with CMs and OEMs seem to indicate satisfaction with
Pb-free HASL performance
 Additional independent, quantitative data should be gathered
 Improved solderability could improve hole fill

46. 46
Pb-Free HASL: Planarity
Recommended minimum thickness
100 min (4 microns)
Lower minimums can result in exposed intermetallic
Primary issue is thickness variability
Greatest variation is among different pad designs
100 min over small pads (BGA bond pads); over 1000 min over large pads
Can be controlled through air knife pressure, pot temperatures, and nickel content

47. Pb-Free HASL: Planarity (cont.)
o Air knives
o Pb-free HASL requires
lower air pressure to
blow off excess solder
o Pot Temperatures
o SnPb: 240C to 260C
o SN100CL: 255C to 270C (air knife temp of 280C)
o Ni content
o Variation can influence fluidity
o Minimum levels critical for planarity
o Some miscommunication as to critical concentrations
Sweatman and Nishimura (IPC APEX 2006)

48. Pb-Free HASL (Composition)
o Minimum Ni concentrations need to be more
clearly specified by licensees
o Nihon recommends >300 ppm
o Recommended maximum Cu concentrations
range from 0.7 to 1.2wt%
o Increased bridging and graininess
o Nihon recommends <0.9wt%
Florida CirTech, www.floridacirtech.com/Databases/pdfs/SN100CL.pdf AIM Solder, www.advprecision.com/pdf/LF_Soldering_Guide.pdf
Balver Zinn, www.cabelpiu.it/user/File/Schede%20prodotto/schede%20nuove%20SN100CL-SN100CLe.pdf

49. Pb-Free HASL: Copper Dissolution
oTo be discussed in detail in solder module
oPresence of nickel is believed to slow the copper dissolution process
oSAC HASL removes ~5 um
oSNC HASL removes ~1 um
www.p-m-services.co.uk/rohs2007.htm
www.pb-free.org/02_G.Sikorcin.pdf
www.evertiq.com/news/read.do?news=3013&cat=8 (Conny Thomasson, Candor Sweden AB)
Nihon Superior

50. Pb-Free HASL: Additional Concerns
oRisk of thermal damage, including warpage and influence on long term reliability (PTH fatigue, CAF robustness)
oNo incidents of cracking / delamination / excessive warpage reported to DfR to date
oShort exposure time (3 to 5 seconds) and minimal temp. differential (+5ºC above SnPb) may limit this effect
oCompatibility with thick (>0.135”) boards
oLimited experimental data (these products are not currently Pb-free)
oMixing of SNC with SAC
oInitial testing indicates no long-term reliability issues (JGPP)

51. Module 5: PCB Robustness Overview Cracking and Delamination

52. 52
Printed Board Robustness Concerns
Increased Warpage
PTH Cracks
Land Separation
Solder Mask Discoloration
Blistering
Delamination
Pad Cratering

53. 53
Printed Board Damage
Predicting printed board damage can be difficult
Driven by size (larger boards tend to experience higher temperatures)
Driven by thickness (thicker boards experience more thermal stress)
Driven by material (lower Tg tends to be more susceptible)
Driven by design (higher density, higher aspect ratios)
Driven by number of reflows
No universally accepted industry model

54. Printed Board Damage: Industry Response
oConcerns with printed board damage have almost entirely been addressed through material changes or process modifications
oNot aware of any OEMs initiating design rules or restrictions
oSpecific actions driven by board size and peak temperature requirements

55. Industry Response (cont.)
oSmall, very thin boards
oUp to 4 x 6 and 62 mil thick
oPeak temperatures as low as 238ºC
oMinimal changes; most already using 150ºC Tg Dicy (tends to be sufficient)
oMedium, thin boards
oUp to 10 x 14 and 75 mil thick
oTend to have moderate-sized components; limits peak temperatures to 245ºC-248ºC
oRigorous effort to upgrade laminate materials (dicy-cured may not be feasible)
oLarge, thick boards
oUp to 18 x 24 and 180 mil thick
oDifficulty in maintaining peak temperatures below 260ºC
oVery concerned
Rothshild, APEX 2007

56. 56
PCB Robustness: Material Selection
Board thickness
IR-240~250℃
Board thickness
IR-260℃
≤60mil
Tg140 Dicy
All HF materials OK
≤ 60mil
Tg150 Dicy
HF- middle and high Tg materials OK
60~73mil
Tg150 Dicy
NP150, TU622-5
All HF materials OK
60~73mil
Tg170 Dicy
HF –middle and high Tg materials OK
73~93mil
Tg170 Dicy, NP150G-HF
HF –middle and high Tg materials OK
73~93mil
Tg150 Phenolic + Filler
IS400, IT150M, TU722-5, GA150
HF –middle and high Tg materials OK
93~120mil
Tg150 Phenolic + Filler
IS400, IT150M, TU722-5
Tg 150
HF –middle and high Tg materials OK
93~130mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo, TU722- 7
HF –middle and high Tg materials OK
121~160mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo
TU722-7
HF –high Tg materials OK
≧131mil
Phenolic Tg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF –high Tg materials OK
≧161mil
PhenolicTg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF material - TBD
≧161mil
TBD – Consult Engineering for specific design review
1.Copper thickness = 2OZ use material listed on column 260 ℃
2.Copper thickness >= 3OZ use Phenolic base material or High Tg Halogen free materials only
3.Twice lamination product use Phenolic material or High Tg Halogen free materials only (includes HDI)
4.Follow customer requirement if customer has his own material requirement
5.DE people have to confirm the IR reflow Temperature profile
J. Beers, Gold Circuits

57. Printed Board Damage: Prevention
oThermal properties of laminate material are primarily defined by four parameters
oOut of plane coefficient of thermal expansion (Z-CTE)
oGlass transition temperature (Tg)
oTime to delamination (T260, T280, T288)
oTemperature of decomposition (Td)
oEach parameter captures a different material behavior
oHigher number slash sheets (> 100) within IPC-4101 define these parameters to specific material categories

58. Thermal Parameters of Laminate
oOut of plane CTE (below Tg or Z-axis: 50ºC to 260ºC)
oCTE for SnPb is 50ppm - 90ppm (50C to 260C rarely considered)
oPb-free: 30ppm - 65ppm or 2.5 – 3.5%
oGlass transition temperature (IPC-TM-650, )
oCharacterizes complex material transformation (increase in CTE, decrease in modulus)
oTg of 110ºC to 170ºC for SnPb
oPb-free: 150ºC to 190ºC
oTime to delamination (IPC-TM-650, 2.4.24.1)
oCharacterizes interfacial adhesion
oT-260 for SnPb is 5-10 minutes
oPb-free: T-280 of 5-10 minutes or T-288 of 3-6 minutes
oTemperature of decomposition (IPC-TM-650, 2.3.40)
oCharacterizes breakdown of epoxy material
oTd of 300ºC for SnPb
oPb-free: Td of 320ºC

59. Thermal Parameters (cont.)
o Strong correlation between Td and T288
o Suggests cohesive failure during T288
o May imply poor ability to capture interfacial weaknesses
B. Hoevel, et. al., New epoxy resins for printed wiring board applications, Circuit World, 2007, vol. 33, no. 2

60. Industry Response: Material Selection
oOEMs are attempting to stay with FR-4 laminate
oSelecting phenolic, filled, higher functionality (higher Tg), CAF- resistant
oSolutions to multiple issues (thermal robustness, Df/Dk) can be found in alternative materials (BT, PPO) or blends
oNot cost justifiable at this time
Moises Cases, IBM (PCB / OS Symposium 2007)

61. PCB Robustness: Material Selection
oThe appropriate material selection is driven by the failure mechanism one is trying to prevent
oCracking and delamination
oPlated through fatigue
oConductive anodic filament formation

62. Delamination / Cracking: Observations
oMorphology and location of the cracking and delamination can vary
oEven within the same board
oFailure morphology and locations
oWithin the middle and edge of the PCB
oWithin prepregs and/or laminate
oWithin the weave, along the weave, or at the copper/epoxy interface (adhesive and cohesive)

63. Delamination / Cracking: Case Study
oDelamination marked by red boxes
oScalloped shape is due to pinning at the plated through holes (PTHs)
oResults from acoustic microscopy confirmed observations from visual inspection
oNo additional delamination sites were identified
A
B

64. Corner Delamination (cont.)
oLack of adhesion to glass fibers (yellow outline)
oCould be initiation site
oMay suggest wetting issues

65. Central Delamination
oDelamination appears to span multiple layers
oPlated through holes pin the expansion of the delamination

66. Additional Observations
oDrivers
oHigher peak temperatures
oIncreasing PCB thickness
oDecreasing via-to-via pitch
oIncreasing foil thickness (1-oz to 2-oz)
oPresence of internal pads
oSequential lamination
oLimited information
oControlled depth drilling
oExtensive debate about root-cause
oNon-optimized process
oIntrinsic limit to PCB capability
oMoisture absorption
Rothschild, IPC APEX 2007
Sequential Lamination

67. Delamination / Cracking: Root-Cause
oNon-Optimized Process
oSome PCB suppliers have demonstrated improvement through modifications to lamination process or oxide chemistry
oSome observations of lot-to-lot variability
oLimit to PCB Capability
oDifficult to overcome adhesion vs. thermal performance tradeoff (dicy vs. phenolic)
oHigh stresses developed during Pb-free exceed material strength of standard board material
oMoisture Absorption

68. Cracking and Moisture Absorption
oDoes moisture play a role?
oNo
oDfR found delamination primarily around the edge and away from PTH sites after MSL testing
oIBM found minimal differences after a 24 hr bake of coupons with heavy copper (>2 oz)
oDelamination / cracking observed in board stored for short (<2 weeks) periods of time
oYes
oDfR customer found improvement after 48 hrs at 125C
oA number of companies now require 5 – 24 hour bake before reflow
oIBM found improvement with coupons with nominal copper
oDfR observed more rapid degradation of boards exposed to moisture, even after multiple reflows
oSome customers specifying maximum moisture absorption
oWhere does the moisture come from?

69. Cracking and Moisture (cont.)
oStorage of prepregs and laminates
oDrilling process
oMoisture is absorbed by the side walls (microcracks?)
oTrapped after plating
oStorage of PCBs at PCB manufacturer
oStorage of PCBs at CCA manufacturer

70. 70
PCB Robustness: Qualifying Printed Boards
oThis activity may provide greatest return on investment
oUse appropriate number of reflows or wave
oIn-circuit testing (ICT) combined with construction analysis (cracks can be latent defect)
o6X Solder Float (at 288C) may not be directly applicable
oNote: higher Tg / phenolic is not necessarily better
oLower adhesion to copper (greater likelihood of delamination)
oGreater risk of drilling issues
oPotential for pad cratering
oHigher reflow and wave solder temperatures may induce solder mask delamination
oEspecially for marginal materials and processes
oMore aggressive flux formulations may also play a role
oNeed to re-emphasize IPC SM-840 qualification procedures

71. Module 6: PCB Robustness PTH Barrel Cracking Conductive Anodic Filaments (CAF)

72. 72
Plated Through Hole (PTH) Fatigue
PTH fatigue is the circumferential cracking of the copper plating that forms the PTH wall
It is driven by differential expansion between the copper plating (~17 ppm) and the out-of- plane CTE of the printed board (~70 ppm)
Industry-accepted failure model
IPC-TR-579

73. 73
PTH Fatigue: Pb-Free

74. PTH and Pb-Free (cont.)
oFindings
oLimited Z-axis expansion and optimized copper plating prevents degradation
oIndustry response
oMovement to Tg of 150 - 170C
oZ-axis expansion between 2.5 to 3.5%

75. Conductive Anodic Filaments (CAF)
oThe migration of copper along a path internal to a printed circuit board or laminate. Driven by temperature, humidity, the applied voltage, and the electric field strength
oCAF can cause current leakage, intermittent electrical shorts and thermal damage

76. 76
CAF: Examples
A
A
A:A Cross-Section

77. 77
CAF: Examples

78. 78
CAF: Examples

79. 79
CAF: Hollow Fibers
Hollow fibers, which form from decomposed impurities in the glass melt, are an alternate path for CAF

80. 80
CAF: Pb-Free
Major concern in telecom/server industry
Frequency of events can increase by two orders of magnitude
Time to failure can drop from >750h to 50h
Initially, no “qualified” printed boards
Focus on specific designs
Large (>12x18) / multilayer (>10)
Fine pitch (0.8, 1.0 mm) ball grid arrays (BGAs)
Solutions?
CAF „resistant‟ laminate
Different epoxy formulations
Higher quality weaves
Phenolic cured epoxy (filled)
Can be much better
Sensitive to drilling
Increased price?
Sometimes, not always

81. Module 7: PCB Robustness Pad Cratering Electro-Chemical Migration (ECM)

82. 82
Pad Cratering
Cracking initiating within the laminate during a dynamic mechanical event
In circuit testing (ICT), board depanelization, connector insertion, shock and vibration, etc.
G. Shade, Intel (2006)

83. 83
Pad Cratering
oDrivers
oFiner pitch components
oMore brittle laminates
oStiffer solders (SAC vs. SnPb)
oPresence of a large heat sink
oDifficult to detect using standard procedures
oX-ray, dye-n-pry, ball shear, and ball pull
Intel (2006)

84. 84
Solutions to Pad Cratering
oBoard Redesign
oSolder mask defined vs. non-solder mask defined
oLimitations on board flexure
o750 to 500 microstrain
oComponent dependent
oMore compliant solder
oSAC305 is relatively rigid
oSAC105 and SNC are possible alternatives
oNew acceptance criteria for laminate materials

85. Laminate Acceptance Criteria
oIntel-led industry effort
oAttempting to characterize laminate material using high-speed ball pull and shear testing
oResults inconclusive to-date
oAlternative approach
oRequire reporting of fracture toughness and elastic modulus

86. 86
Is Pad Cratering a Pb-Free Issue?
Paste Solder Ball
Average Fracture
Load (N)
Std Dev (N)
SnPb SnPb 692 93
SnPb 656 102
Sn4.0Ag0.5Cu 935 190
Sn4.0Ag0.5Cu
35x35mm, 388 I/O BGA; 0.76 mm/min
Roubaud, HP
APEX 2001

87. 87
Electro-Chemical Migration: Overview
oInsidious failure mechanism
oSelf-healing: leads to large number of no-trouble-found (NTF)
oCan occur at nominal voltages (5 V) and room conditions (25C, 60%RH)
oDue to the presence of contaminants on the surface of the board
oStrongest drivers are halides (chlorides and bromides)
oWeak organic acids (WOAs) and polyglycols can also lead to drops in the surface insulation resistance
oPrimarily controlled through controls on cleanliness
oMinimal differentiation between existing Pb-free solders, SAC and SnCu, and SnPb
oOther Pb-free alloys may be more susceptible (e.g., SnZn)
elapsed time 12 sec.

88. Cleanliness Recommendations
Ion
Control
Maximum
Fluoride
N/A
1 mg/in2
Chloride
2 mg/in2
4.5 mg/in2
Bromide
10 mg/in2
15 mg/in2
Nitrates, Sulfates
2 – 4 mg/in2
6 – 12 mg/in2
WOAs
150 mg/in2
250 mg/in2

89. Module 8: Solders Discussion of 2nd gen alloys (e.g., SN100C) Intermetallic formation

90. Divergence in Solder Selection
oConsiderations include
oPRICE!
oInsufficient performance
oNewly identified failure mechanisms
oMarket still unsteady; proliferation and evolution of material sets
oSolder seeing the fastest increase in market share?
oSnCu+Ni (SNC)
SAC405
SAC305
SAC105
SACX
SNC
SnAg
SNCX
SnCu
SnAgCu
??

91. The Current State of Lead-Free
oComponent suppliers
oSAC305 still dominant, but with increasing introduction of low silver alloys (SAC205, SAC105, SAC0507)
oSolder Paste
oSAC305 still dominant
oWave and Rework
oSn07Cu+Ni (SN100C)
oSn07Cu+Co (SN100e)
oSn07Cu+Ni+Bi (K100LD)
oHASL PCB Coating
oSn07Cu+Ni (SN100C)

92. Solder Trends
oSAC305 dominates surface mount reflow (SMT)
oSAC105 increasingly being used in area array components in mobile applications
oSNC pervasive in wave solder and HASL
oIncreasing acceptance in Japan for SMT
oIntensive positioning for “X” alloys (SACX, SNCX)
K-W Moon et al, J. Electronic Materials, 29 (2000) 1122-1236

93. What are Solder Suppliers Promoting?
Company
Paste
Wire / Wave
Senju
ECO Solder (SAC305)
Nihon Genma
NP303 (SAC305),
NP601 (Sn8Zn3Bi)
NP303 (SAC305),
NP103 (SAC0307)
Metallic Resources
SAC305
SAC305,
SC995e (Sn05Cu+Co)
Koki
S3X (SAC305),
S3XNI58 (SAC305+Ni+In),
SB6N58 (Sn3.5Ag0.5Bi6In)
S3X (SAC305),
S03X7C (SAC0307+0.03Co)
Heraeus
SAC405
Cookson / Alpha Metals
SACX (SAC0307+Bi+0.1P+0.02RareEarth+0.01Sb)
Kester
K100LD (Sn07Cu+0.05Ni+Bi)
Qualitek
SN100e (Sn07Cu+0.05Co)
Nihon Superior
SN100C (Sn07Cu+0.05Ni+Ge)
AIM
SN100C (Sn07Cu+0.05Ni+Ge)
Indium
Indium5.1AT (SAC305)
N/A
Amtech
SAC305, Sn3.5Ag, Sn5Ag, Sn07Cu, Sn5Sb
Shenmao
SAC305 to SAC405, SAC305+0.06Ni+0.01Ge
Henkel
No preference
EFD
No preference
P. Kay Metals
No preference

94. 94
Intermetallic Basics
oTin and copper bond to form intermetallics of Cu3Sn and Cu6Sn5
oIrreversible
oOccurs rapidly in the liquid state, but rate still appreciable in solid state (even at room temperature)
oTotal intermetallic thickness after all assembly and rework should be between 1 to 4 um
oElements
oBi is in solid solution in the tin-rich phase or precipitates out (>1%)
oIn will form binary intermetallic species with Ag and Cu and ternary intermetallic species SnAgIn and SnCuIn
oCo seems to display similar behavior to Ni

95. 95
Intermetallic Growth
Cu3Sn Layer
Cu6Sn5 Layer
Cu pad
Solder

96. Intermetallic Growth (cont.)
Sn3.8Ag0.7Cu / OSP
Yoon, JEM 2004
0 2 4 6 8 10 12
0
2
4
6
IMC Thickness (mm)
t1/2 (hr1/2)
185C
130C, 150C
Sn3.5Cu0.7Cu / ENIG
Lim, ECTC 2003
Pang, JEM 2004
119C
143C
168C
E = 0.51, 0.53 eV
Zheng, ECTC 2002
Liao, JEM 2004 E = 0.97 eV
Henshall, APEX 2001

97. IMC Thickness Model vs Measured Data
exp( / ) 0 D D E kT
Z Dt
A  

Fick‟s Law of
Diffusion:
Fitting the
original data set
to the derived
diffusion
coefficient (D0 =
5851) and
activation energy
(EA = 0.556eV/K)
shows strong
0 correlation
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 200 400 600 800 1000 1200
Hours Aged
um of IMC
100C
125C
150C
Predicted - 150C
Predicted - 125C
Predicted - 100C

98. Intermetallic Growth Effects
oChanges in electrical resistance
oMinimal
oChanges in shear strength
oMinimal
oChanges in pull strength
oMinimal
Sn0.5Cu / ENIG
Sn3.8Ag0.7Cu / OSP

99. Module 9: Solders Copper Dissolution Mixed Assembly

100. 100
Solders: Copper Dissolution
The reduction or elimination of surface copper conductors due to repeated exposure to Sn-based solders
Significant concern for industries that perform extensive rework
Telecom, military, avionics
Bath, iNEMI
ENIG Plating 60 sec. exposure 274ºC solder fountain

101. 101
Solders: Copper Dissolution (cont.)
oPTH knee is the point of greatest plating reduction
oPrimarily a rework/repair issue
oCelestica identified significant risk with >1X rework
oAlready having a detrimental effect
oMajor OEM unable to repair ball grid arrays (BGAs)
S. Zweigart, Solectron

102. Copper Dissolution (Contact Time)
oContact time is the major driver
oSome indications of a 25-30 second limit
oPreheat and pot temp. seem to have a lesser effect
oOptimum conditions (for SAC)
oContact time (max): 47 sec. (cumulative)
oPreheat temperature: 140-150°C
oPot temperature: 260-265°C
A Study of Copper Dissolution During Pb-Free PTH Rework Using a Thermally Massive Test Vehicle , C. Hamilton (May 2007)

103. Contact Time (cont.)
oCopper Erosion During Assembly By Lead Free Solder (HDPUG)

104. 104
Solutions to Cu Dissolution
oOption 1: restriction on rework
oNumber of reworks or contact time
oOption 2: solder material
oIndications that SNC can decrease dissolution rates
oReduced diffusion rate through Sn-Ni-Cu intermetallics
oOption 3: board plating
oSome considering ENIG
oSome considering SNC HASL
A Study of Copper Dissolution During Pb-Free PTH Rework Using a Thermally Massive Test Vehicle , C. Hamilton (May 2007)

105. 105
Dissolution: Copper vs. Nickel
o Nickel (Ni) plating has a dissolution rate approximately
1/10th of copper (Cu) plating
o Given similar solder temperatures and contact times
Albrecht, SMTA 2006 Albrecht, SMTA 2006

106. 106
Mixed Assembly
Primarily refers to Pb-free BGAs assembled using SnPb eutectic solder paste
Why?
Area array devices (e.g., ball grid array, chip scale package) with eutectic solder balls are becoming obsolete
Military, avionics, telecommunications, industrial do not want to transition to Pb- free…..yet
UIC

107. 107
SnPb BGAs and the Component Industry
For certain device types, Hi-Rel dominates market share
Mil/Aero is ~10% of Hi-Rel
Hi-Rel products tend to be of higher value
Greater profit for part suppliers
Prismark, iNEMI SnPb-Compatible BGA Workshop (IPC/APEX 2007)

108. 108
SnPb BGAs – Supplier Response
Result is wide variation in SnPb BGA availability
Driven by market (Micron)
SDR SDRAM preferred by Hi-Rel (low Pb-free penetration)
DDR SDRAM preferred by Computers (high Pb-free penetration), though SnPb available past 2011
Driven by lifecycle (Freescale)
Legacy FC-BGAs are primarily SnPb; new FC-BGAs are primarily Pb-free
iNEMI SnPb-Compatible BGA Workshop (IPC/APEX 2007)

109. 109
Mixed Assembly: Reflow
Initial studies focused on peak temperature
Identified melt temperature of solder ball as critical parameter
217°C for SAC305
Ensured ball collapse and intermixing
Recommendations
Minimum peak reflow temperature of 220°C
Reflow temperatures below 220°C may result in poor assembly yields and/or inadequate interconnect reliability
For increased margin, >225 to 245°C peak

110. 110
Mixed Assembly: Solder Joint Morphology
Motorola

111. 111
Mixed Assembly: Peak Temp Statements
Cisco Systems: > 210°C
Formation of SnPbAg phase (Tm = 179°C) may allow for lower reflow temperatures
Intel: > 217°C
Infineon: 215 - 230°C
220°C peak used in exceptional circumstances
230°C peak recommended
IBM: 245°C
Minimum time above liquidus (TAL) of 80 seconds
Need to watch for voiding
Talk to your paste supplier

112. 112
Mixed Assembly: Time Above Liquidus
Effect is inconclusive
Kinyanjui, Sanmina-SCI, iNEMI SnPb-Compatible BGA Workshop (IPC/APEX 2007)

113. 113
Mixed Assembly: Solder Paste Volume
Some conflict
Sanmina claims no effect
Celestica claims significant effect
Other factors may play a greater role
Additional investigation necessary
Snugovsky, Celestica (2005)
Moderate solder paste volume
Large solder paste volume
Kinyanjui, Sanmina-SCI, iNEMI SnPb-Compatible BGA Workshop (IPC/APEX 2007)

114. 114
Mixed Assembly: Effect of Pitch
Intel: reduced self alignment
Degree of difficulty: 0.5mm > 0.8mm > 1 - 1.27mm pitch component
Sanmina: improved mixing
Kinyanjui, Sanmina-SCI, iNEMI SnPb-Compatible BGA Workshop (IPC/APEX 2007)

115. 115
Mixed Assembly: Temp Cycling Results
10 100 1,000 8,000
0.03
0.3
3
30
99
SnAgCu/SnPb
SnAgCu/SnAgCu
SnPb
Cycles to Failure
Cumulative Failure (%)
HP: 0 to 100ºC, 214ºC Peak Temp

116. Mixed Assembly (Other)
oiNEMI recently reported issues with low silver (Ag) Pb- free alloys
oSAC105, SAC0307, etc.
oHigh pasty range creates voiding and shrinkage cracks
oMixed assembly with low-silver SAC is not recommended

117. 117
Mixed Assembly: Conclusions
oA potentially lower risk than complete transition to Pb- free
oImportant note: more studies on vibration and shock performance should be performed
oThe preferred approach for some high reliability manufacturers (military, telecom):
oAcceptance of mixed assembly could be driven by GEIA-STD- 0005-1

118. 118
Mixed Assembly: Alternatives
oOther options on dealing with Pb-free BGAs other than mixing with SnPb
oPlacement post-reflow
oTwo flux options
oApplication of Pb-free solder paste
oApplication of flux preform
oTwo soldering options
oHot air (manual)
oLaser soldering (automatic)

119. Thank you!
Any Questions?
ctulkoff@dfrsolutions.com
www.dfrsolutions.com