Placement

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This is the basic presentation of placement flow which was prepared by me.

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  • Scan chains are again connected after performing the clock tree synthesis.
  • Placement

    1. 1. PLACEMENT PHYSICAL DESIGN
    2. 2. Prerequisite • Must be aware of the floor planning and the power planning concepts. • Must be aware of the commonly used terms and basic design. • This presentation will help you to get the placement related knowledge of a design.
    3. 3. GOALS • Design goals can be timing, power and area. • Guarantee the router can complete the routing step • Minimize all the critical net delays • Make the chip as dense as possible
    4. 4. DISCUSSIONS • What is placement and its need in physical design. • What is pre, in, post placement optimization stages. • Additional constraints to improve placement related issues.
    5. 5. ZERO INTERCONNECT TIMING ANALYSIS • Before you start with placement:  Perform a 'Timing Sanity Check' or ‘zero interconnect timing analysis’.  Check the violations If zero violations : Continue on to placement If still violating: Go back to Synthesis!
    6. 6. Placement flow in the physical design Design setup and floor plan data Detach scan chain Set Placement options Auto place Congestion OK ? Timing OK ? Perform ctsAdditional optimization NO YES YES No
    7. 7. SCAN CHAIN HANDLING • Disconnect the scan chains prior to placement to focus on the functional critical paths. • If serially connected FFs are placed far apart this may require a lot more routing resources than necessary. • If FFs are placed close together, according to their scan chain ordering, this may hurt timing along functional critical paths. • Scan chains will be reconnected after CTS  Same grouping of FFs  Different ordering: based on placement, to minimize routing resources
    8. 8. Specify • The Place menu’s Specify forms enable you to specify and assign spare cells, scan cells, JTAG cells, and placement blockage for power and ground stripes. You must assign these objects before running placement. • The Specify submenu provides access to the following features:  Spare cells  Cell paddings  Jtag cells  Placement blockages
    9. 9. PLACEMENT • Before the start of placement optimization all Wire Load Models (WLM) are removed. Placement uses RC values from Virtual Route (VR) to calculate timing. • VR is the shortest Manhattan distance between two pins. • VR RCs are more accurate than WLM RCs. • Placement is performed in four optimization phases:  Pre-placement optimization  In placement optimization  Post Placement Optimization (PPO) before clock tree synthesis (CTS)  PPO after CTS.
    10. 10. PRE PLACEMENT OPT • Optimizes the netlist before placement, HFNs are collapsed. • It can also downsize the cells.
    11. 11. IN PLACEMENT OPT • Re-optimizes the logic based on VR. • This can perform cell sizing, cell moving, cell bypassing, net splitting, gate duplication, buffer insertion, area recovery. • Optimization performs iteration of setup fixing, incremental timing and congestion driven placement.
    12. 12. PPO BEFORE CTS • Before CTS performs netlist optimization with ideal clocks. • It can fix setup, hold, max trans/cap violations. • It can do placement optimization based on global routing. • It re does HFN synthesis.
    13. 13. PPO AFTER CTS • After CTS optimizes timing with propagated clock. • It tries to preserve clock skew.
    14. 14. What Does it mean if TNS >>WNS? • A large TNS implies that there could be many sub-critical violations that are almost as bad as the critical path violation. • It is also possible that these paths are related or share logic. • We can verify by analyzing the sub-critical paths with detailed timing reports.
    15. 15. What does Optimization Do By Default? • By default, logic optimization during placement works only on the critical path of each clock domain, and stops when it cannot further improve its timing. • Sub-critical paths are not optimized in this stage of optimization.
    16. 16. Critical Range Optimization • Critical Range Optimization (CRO) works on the sub critical paths, which reduces the total number of violations paths and the TNS. • CRO may also help to reduce the critical path violations if it is 'related‘ to some of the sub-critical paths
    17. 17. Goals for placement optimization • Performance : Such as Timing • Logical DRC’S • Routability or congestion • Area • Leakage Power
    18. 18. Some commands used in cadence

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