Xilkernel
Ing. Vincent Claes
Inleiding
OS?
Single-task OS
Multi-Tasking en Multi-User OS
Process and Threads
Memory and Storage
Networks: Services and protocols
TCP/IP Networks
Security: design considerations
XMK + MPSoC
Xilkernel - overview
Small, robust and modular kernel
RTOS
POSIX API
Microblaze, PowerPC
Xilinx Platform Studio (EDK)
Light-weight (16 – 32 kb)
Xilkernel – Why use a kernel?
Typical embedded applications
Various tasks in particular sequence or schedule
Tasks → individual applications on a operating system (OS) is much more intuitive
Enables you to write code at an abstract level
Xilkernel – Why use a kernel?
Many applications rely on OS services like
file systems,
time management,
and so forth.
Xilkernel is a thin library that provides these essential services. Porting or using common and open source libraries (such as graphics or network protocols) might require some form of these OS services.
Xilkernel - Configuration
Configuration
“Software Platform Settings”
Kernel starts by calling xilkernel_main()
Code after this → never reached
Include library “xmk.h” as first library
Xilkernel - Organization
Xilkernel Development Flow
Xilkernel Process Model
Units of execution within xilkernel: process contexts
Scheduling done at process context level
POSIX threads API is primary user-visible interface to process contexts
Interfaces allow creating, destroying and manipulating created application threads (see Xilkernel API)
Threads manipulated with thread identifiers
Underlying process context is identified with process identifier pid_t
Xilkernel scheduling model
Xilkernel
Priority-driven, preemptive scheduling with time slicing (SCHED_PRIO)
Simple Round-robin scheduling (SCHED_RR)
Cannot be changed on a per-thread basis.
Configured statically (at kernel generation time)
Xilkernel scheduling model
SCHED_RR
Single ready queue
Each process context executes for a configured time slice before yielding execution to the next process context in the queue
Xilkernel scheduling model
SCHED_PRIO
As many ready queues as there are priority levels
Priority 0 → highest priority
Higher values → lower priority
Xilkernel scheduling model
SCHED_PRIO
Xilkernel – Process Context States
Each process context
PROC_NEW
A newly created process
PROC_READY
A process ready to execute
PROC_RUN
A process that is running
PROC_WAIT
A process that is blocked on a resource
PROC_DELAY
A process that is waiting for a timeout
PROC_TIMED_WAIT
A process that is blocked on a resource and has an associated timeout
Xilkernel – Process Context States
Xilkernel - Features
Supplies programmer extra abstracted advanced functionality
Thread Management
Semaphores
Message Queues
Shared Memory
Mutex Locks
Dynamic Buffer Memory Management
Software Timers
User-Level Interrupt Handling APIs
ELF Process Management (Deprecated)
Non-lineair execution !
Controlled resource sharing
Xilkernel - Threading
Thread (in xilkernel): a function that is not necessarily processed linearly
Threads are coded like functions, but can work “in parallel”
Threads
Interacting with each other
Pass data back and forth
Xilkernel - Threading
At least one thread required to spawn from the system at kernel start
Main threads → void* without inputs
“OS and Libraries”
“config_pthread_support”
static_pthread_table
Xilkernel - Threading
Xilkernel
2 scheduling modes
SCHED_PRIO
Priority based scheduling
Lower priority threads will always yield to higher priority threads (lower priority number) untill higher priority thread finishes or pthread-joining is used
If 2 threads with same priority → round-robin based scheduling
SCHED_RR
Round-Robin based scheduling
All threads must be processed at close-to the same time. (“parallel”)
Xilkernel - Threading
Pthread support
pthread_create()
pthread_exit()
pthread_join()
pthread_attr_init()
pthread_setschedparam()
Xilkernel – Thread Management
Xilkernel
Basic POSIX threads API
Thread creation and manipulation in st
Enabling new protocol processing with DPDK using Dynamic Device PersonalizationMichelle Holley
Abstract: Dynamic Device Personalization allows a DPDK application to enable identification of new protocols, for example, GTP, PPPoE, QUIC, without changing the hardware. The demo showcases a DPDK application identifying and spreading traffic on GTP and QUIC. Dynamic Device Personalization can be used on any OS supported by DPDK, for example we showcase a QUIC protocol classification demo on Windows OS.
Speaker Bio: Brian Johnson is a Solutions Architect for Intel Ethernet products focusing on network packet processing, virtualization and NFV technologies. He is responsible for the definition and development of networking best practices for cloud and NFVi deployment technologies. Brian jhas over 20 years of experience in server and network product planning during which he held various positions in strategic planning, technical product marketing, and product development.
Prior to joining Intel in 1999, Brian held various technical and marketing roles for computer VARs and was the IT Administrator at the Daily Journal of Commerce in Portland, Oregon. He also served as the Vice Chair for the CompTIA Server+ and council member for CompTIA+ industry certifications.
Brian holds Bachelor of Science degree from Portland State University. Additionally, he has various technology certifications, CompTIA – A+, Server+, and Network+ and am FKA Certified Master Trainer.
HKG15-107: ACPI Power Management on ARM64 Servers (v2)Linaro
HKG15-107: ACPI Power Management on ARM64 Servers
---------------------------------------------------
Speaker: Ashwin Chaugule
Date: February 9, 2015
---------------------------------------------------
★ Session Summary ★
Status of CPPC with runtime PM and discussion on idle PM with ACPI
--------------------------------------------------
★ Resources ★
Pathable: https://hkg15.pathable.com/meetings/250767
Video: https://www.youtube.com/watch?v=eDDgYIkUHLI
Etherpad: http://pad.linaro.org/p/hkg15-107
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2015 - #HKG15
February 9-13th, 2015
Regal Airport Hotel Hong Kong Airport
---------------------------------------------------
http://www.linaro.org
http://connect.linaro.org
Enabling new protocol processing with DPDK using Dynamic Device PersonalizationMichelle Holley
Abstract: Dynamic Device Personalization allows a DPDK application to enable identification of new protocols, for example, GTP, PPPoE, QUIC, without changing the hardware. The demo showcases a DPDK application identifying and spreading traffic on GTP and QUIC. Dynamic Device Personalization can be used on any OS supported by DPDK, for example we showcase a QUIC protocol classification demo on Windows OS.
Speaker Bio: Brian Johnson is a Solutions Architect for Intel Ethernet products focusing on network packet processing, virtualization and NFV technologies. He is responsible for the definition and development of networking best practices for cloud and NFVi deployment technologies. Brian jhas over 20 years of experience in server and network product planning during which he held various positions in strategic planning, technical product marketing, and product development.
Prior to joining Intel in 1999, Brian held various technical and marketing roles for computer VARs and was the IT Administrator at the Daily Journal of Commerce in Portland, Oregon. He also served as the Vice Chair for the CompTIA Server+ and council member for CompTIA+ industry certifications.
Brian holds Bachelor of Science degree from Portland State University. Additionally, he has various technology certifications, CompTIA – A+, Server+, and Network+ and am FKA Certified Master Trainer.
HKG15-107: ACPI Power Management on ARM64 Servers (v2)Linaro
HKG15-107: ACPI Power Management on ARM64 Servers
---------------------------------------------------
Speaker: Ashwin Chaugule
Date: February 9, 2015
---------------------------------------------------
★ Session Summary ★
Status of CPPC with runtime PM and discussion on idle PM with ACPI
--------------------------------------------------
★ Resources ★
Pathable: https://hkg15.pathable.com/meetings/250767
Video: https://www.youtube.com/watch?v=eDDgYIkUHLI
Etherpad: http://pad.linaro.org/p/hkg15-107
---------------------------------------------------
★ Event Details ★
Linaro Connect Hong Kong 2015 - #HKG15
February 9-13th, 2015
Regal Airport Hotel Hong Kong Airport
---------------------------------------------------
http://www.linaro.org
http://connect.linaro.org
The Linux Kernel Scheduler (For Beginners) - SFO17-421Linaro
Session ID: SFO17-421
Session Name: The Linux Kernel Scheduler (For Beginners) - SFO17-421
Speaker: Viresh Kumar
Track: Power Management
★ Session Summary ★
This talk will take you through the internals of the Linux Kernel scheduler.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/sfo17/sfo17-421/
Presentation:
Video: https://www.youtube.com/watch?v=q283Wm__QQ0
---------------------------------------------------
★ Event Details ★
Linaro Connect San Francisco 2017 (SFO17)
25-29 September 2017
Hyatt Regency San Francisco Airport
---------------------------------------------------
Keyword:
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
Agenda:
In this talk we will present various locking mechanisms implemented in the linux kernel.
From System V locks to raw spinlocks and the RT patch.
Speaker:
Mark Veltzer - CTO of Hinbit and a senior instructor at John Bryce. Mark is also a member of the Free Source Foundation and contributes to many free projects.
https://github.com/veltzer
Embedded Systems are basically Single Board Computers (SBCs) with limited and specific functional capabilities. All the components that make up a computer like the Microprocessor, Memory Unit, I/O Unit etc. are hosted on a single board. Their functionality is subject to constraints, and is embedded as a part of the complete device including the hardware, in contrast to the Desktop and Laptop computers which are essentially general purpose (Read more about what is embedded system). The software part of embedded systems used to be vendor specific instruction sets built in as firmware. However, drastic changes have been brought about in the last decade driven by the spurt in technology, and thankfully, the Moore’s Law. New, smaller, smarter, elegant but more powerful and resource hungry devices like Smart-phones, PDAs and cell-phones have forced the vendors to make a decision between hosting System Firmware or full-featured Operating Systems embedded with devices. The choice is often crucial and is decided by parameters like scope, future expansion plans, molecularity, scalability, cost etc. Most of these features being inbuilt into Operating Systems, hosting operating systems more than compensates the slightly higher cost overhead associated with them. Among various Embedded System Operating Systems like VxWorks, pSOS, QNX, Integrity, VRTX, Symbian OS, Windows CE and many other commercial and open-source varieties, Linux has exploded into the computing scene. Owing to its popularity and open source nature, Linux is evolving as an architecturally neutral OS, with reliable support for popular standards and features
We are one of the best embedded systems training institute for advance courses. We are the pioneer of the embedded system training in Pune & Pcmc with the expertise of over 16 years. we are working in the field training & development of embedded systems & currently we are also working on live projects as per the requirements of clients. though we provide many different courses & training in embedded all aim at giving good practical knowledge to students as well help them in their career.
- Use of EtherCAT technology at PXL TECH department.
- Use of Beckhoff modules
- Implementation of EtherCAT core on Xilinx FPGA
- Use of piggyback boards
The Linux Kernel Scheduler (For Beginners) - SFO17-421Linaro
Session ID: SFO17-421
Session Name: The Linux Kernel Scheduler (For Beginners) - SFO17-421
Speaker: Viresh Kumar
Track: Power Management
★ Session Summary ★
This talk will take you through the internals of the Linux Kernel scheduler.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/sfo17/sfo17-421/
Presentation:
Video: https://www.youtube.com/watch?v=q283Wm__QQ0
---------------------------------------------------
★ Event Details ★
Linaro Connect San Francisco 2017 (SFO17)
25-29 September 2017
Hyatt Regency San Francisco Airport
---------------------------------------------------
Keyword:
'http://www.linaro.org'
'http://connect.linaro.org'
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961
Agenda:
In this talk we will present various locking mechanisms implemented in the linux kernel.
From System V locks to raw spinlocks and the RT patch.
Speaker:
Mark Veltzer - CTO of Hinbit and a senior instructor at John Bryce. Mark is also a member of the Free Source Foundation and contributes to many free projects.
https://github.com/veltzer
Embedded Systems are basically Single Board Computers (SBCs) with limited and specific functional capabilities. All the components that make up a computer like the Microprocessor, Memory Unit, I/O Unit etc. are hosted on a single board. Their functionality is subject to constraints, and is embedded as a part of the complete device including the hardware, in contrast to the Desktop and Laptop computers which are essentially general purpose (Read more about what is embedded system). The software part of embedded systems used to be vendor specific instruction sets built in as firmware. However, drastic changes have been brought about in the last decade driven by the spurt in technology, and thankfully, the Moore’s Law. New, smaller, smarter, elegant but more powerful and resource hungry devices like Smart-phones, PDAs and cell-phones have forced the vendors to make a decision between hosting System Firmware or full-featured Operating Systems embedded with devices. The choice is often crucial and is decided by parameters like scope, future expansion plans, molecularity, scalability, cost etc. Most of these features being inbuilt into Operating Systems, hosting operating systems more than compensates the slightly higher cost overhead associated with them. Among various Embedded System Operating Systems like VxWorks, pSOS, QNX, Integrity, VRTX, Symbian OS, Windows CE and many other commercial and open-source varieties, Linux has exploded into the computing scene. Owing to its popularity and open source nature, Linux is evolving as an architecturally neutral OS, with reliable support for popular standards and features
We are one of the best embedded systems training institute for advance courses. We are the pioneer of the embedded system training in Pune & Pcmc with the expertise of over 16 years. we are working in the field training & development of embedded systems & currently we are also working on live projects as per the requirements of clients. though we provide many different courses & training in embedded all aim at giving good practical knowledge to students as well help them in their career.
- Use of EtherCAT technology at PXL TECH department.
- Use of Beckhoff modules
- Implementation of EtherCAT core on Xilinx FPGA
- Use of piggyback boards
A presentation on the technology of thread and seams, including thread and needle types, sizing conventions, seam and stitch types, and trouble shooting.
"ZYNQ-7000 High Performance Electric Drive and Silicon Carbide Multilevel inverter with Scilab Hardware-in-the-loop"
By Giulio Corradi, Xilinx for ScilabTEC 2015
This presentation by Stanislav Donets (Lead Software Engineer, Consultant, GlobalLogic, Kharkiv) was delivered at GlobalLogic Kharkiv C++ Workshop #1 on September 14, 2019.
In this talk were covered:
- Graphics Processing Units: Architecture and Programming (theory).
- Scratch Example: Barnes Hut n-Body Algorithm (practice).
Conference materials: https://www.globallogic.com/ua/events/kharkiv-cpp-workshop/
Slides that accompanied a three-hour crash training course on sysadmin survival skills useful for sysadmins of Evergreen open source library software. Session led by Don McMorris, Equinox Software.
I think this presentation about Adapteva's Parallella is one of the most comprehensive till now. Feel free to use it. I gave this talk on 10th Dec 2014 at Cloud Research Lab, Ericsson AB, Lund, Sweden.
System Device Tree and Lopper: Concrete Examples - ELC NA 2022Stefano Stabellini
System Device Tree is an extension to Device Tree to describe all the hardware on an SoC, including heterogeneous CPU clusters and secure resources not typically visible to an Operating System like Linux. This full view allows the System Device Tree to be the "One true source" of the entire hardware description and helps to prevent the common (and hard-to-debug) problem of conflicting resources and system consistency. Lopper is an Open Source framework to parse and manipulate System Device Tree. With Lopper, it is possible to generate multiple traditional Device Trees from a single larger System Device Tree. This presentation will provide an overview of System Device Tree and will discuss the latest updates of the specification and tooling. The talk will illustrate multiple use-cases for System Device Tree with concrete examples, such as Linux running on the more powerful CPU cluster and Zephyr running on a smaller Cortex-R cluster. It will also show how to use Lopper to generate multiple traditional Device Trees targeting different OSes, not just Linux but also Zephyr/other RTOSes. Finally, an end-to-end demo based on Yocto to build a complete heterogeneous system with multiple OSes and RTOSes running on different clusters on a single reference board will be shown.
At a time when Herbt Sutter announced to everyone that the free lunch is over (The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software), concurrency has become our everyday life.A big change is coming to Java, the Loom project and with it such new terms as "virtual thread", "continuations" and "structured concurrency". If you've been wondering what they will change in our daily work or
whether it's worth rewriting your Tomcat-based application to super-efficient reactive Netty,or whether to wait for Project Loom? This presentation is for you.
I will talk about the Loom project and the new possibilities related to virtual wattles and "structured concurrency". I will tell you how it works and what can be achieved and the impact on performance
cachegrand: A Take on High Performance CachingScyllaDB
cachegrand is what happens when you throw in a mix a SIMD-accelerated hashtable — capable of performing parallel GET operations without locks or busy-wait loops (e.g. atomic operations) — with fibers, io_uring, your own I/O library, your own memory allocator, and an in-memory & on-disk time series database!
Written in C, built from scratch, natively modular - currently working on Redis compatibility — it's a platform that can deliver very high QPS with low latencies for caching and data streaming with the door open to supporting business logic in Rust & WebAssembly down the line.
This session will focus on developing techniques and OS components used highlighting how they can provide an extra boost to your platforms, no matter the programming language.
Taming Non-blocking Caches to Improve Isolation in Multicore Real-Time SystemsHeechul Yun
In this paper, we show that cache partitioning does
not necessarily ensure predictable cache performance in modern
COTS multicore platforms that use non-blocking caches to exploit
memory-level-parallelism (MLP).
Through carefully designed experiments using three real COTS
multicore platforms (four distinct CPU architectures) and a cycleaccurate
full system simulator, we show that special hardware
registers in non-blocking caches, known as Miss Status Holding
Registers (MSHRs), which track the status of outstanding cachemisses,
can be a significant source of contention; we observe up
to 21X WCET increase in a real COTS multicore platform due
to MSHR contention.
We propose a hardware and system software (OS) collaborative
approach to efficiently eliminate MSHR contention for
multicore real-time systems. Our approach includes a low-cost
hardware extension that enables dynamic control of per-core
MLP by the OS. Using the hardware extension, the OS scheduler
then globally controls each core’s MLP in such a way that
eliminates MSHR contention and maximizes overall throughput
of the system.
We implement the hardware extension in a cycle-accurate fullsystem
simulator and the scheduler modification in Linux 3.14
kernel. We evaluate the effectiveness of our approach using a set
of synthetic and macro benchmarks. In a case study, we achieve
up to 19% WCET reduction (average: 13%) for a set of EEMBC
benchmarks compared to a baseline cache partitioning setup.
Step by Step tutorial on the implementation of FreeRTOS on AVNET MiniZED Board. This board is powered by a Xilinx Zynq FPGA (7007S).
This manual uses Xilinx Vitis Environment.
Implementing an interface in r to communicate with programmable fabric in a x...Vincent Claes
This paper shows the details for implementing an interface between the programming language R and programmable fabric of a Xilinx Zynq FPGA on a zedboard.
Debugging IoT Sensor Interfaces (SPI) with Digilent Analog Discovery 2Vincent Claes
Tutorial on how to debug a SPI Peripheral with the Digilent Analog Discovery 2.
We create a SPI Master with the Discovery and use an Olimex MOD-LED8x8RGB Matrix as device under test.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Climate Impact of Software Testing at Nordic Testing DaysKari Kakkonen
My slides at Nordic Testing Days 6.6.2024
Climate impact / sustainability of software testing discussed on the talk. ICT and testing must carry their part of global responsibility to help with the climat warming. We can minimize the carbon footprint but we can also have a carbon handprint, a positive impact on the climate. Quality characteristics can be added with sustainability, and then measured continuously. Test environments can be used less, and in smaller scale and on demand. Test techniques can be used in optimizing or minimizing number of tests. Test automation can be used to speed up testing.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
Discover how Standard Chartered Bank harnessed the power of Neo4j to transform complex data access challenges into a dynamic, scalable graph database solution. This keynote will cover their journey from initial adoption to deploying a fully automated, enterprise-grade causal cluster, highlighting key strategies for modelling organisational changes and ensuring robust disaster recovery. Learn how these innovations have not only enhanced Standard Chartered Bank’s data infrastructure but also positioned them as pioneers in the banking sector’s adoption of graph technology.
Dr. Sean Tan, Head of Data Science, Changi Airport Group
Discover how Changi Airport Group (CAG) leverages graph technologies and generative AI to revolutionize their search capabilities. This session delves into the unique search needs of CAG’s diverse passengers and customers, showcasing how graph data structures enhance the accuracy and relevance of AI-generated search results, mitigating the risk of “hallucinations” and improving the overall customer journey.
GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...Neo4j
Leonard Jayamohan, Partner & Generative AI Lead, Deloitte
This keynote will reveal how Deloitte leverages Neo4j’s graph power for groundbreaking digital twin solutions, achieving a staggering 100x performance boost. Discover the essential role knowledge graphs play in successful generative AI implementations. Plus, get an exclusive look at an innovative Neo4j + Generative AI solution Deloitte is developing in-house.
Unlocking Productivity: Leveraging the Potential of Copilot in Microsoft 365, a presentation by Christoforos Vlachos, Senior Solutions Manager – Modern Workplace, Uni Systems
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
2. Inleiding
• OS?
• Single-task OS
• Multi-Tasking en Multi-User OS
• Process and Threads
• Memory and Storage
• Networks: Services and protocols
• TCP/IP Networks
• Security: design considerations
• XMK + MPSoC
3. Xilkernel - overview
• Small, robust and modular kernel
• RTOS
• POSIX API
• Microblaze, PowerPC
• Xilinx Platform Studio (EDK)
• Light-weight (16 – 32 kb)
4. Xilkernel – Why use a kernel?
• Typical embedded applications
– Various tasks in particular sequence or
schedule
• Tasks → individual applications on a
operating system (OS) is much more
intuitive
• Enables you to write code at an
abstract level
5. Xilkernel – Why use a kernel?
• Many applications rely on OS services
like
– file systems,
– time management,
– and so forth.
• Xilkernel is a thin library that provides
these essential services. Porting or using
common and open source libraries (such
as graphics or network protocols) might
require some form of these OS services.
6. Xilkernel - Configuration
• Configuration
– “Software Platform Settings”
• Kernel starts by calling
xilkernel_main()
– Code after this → never reached
• Include library “xmk.h” as first library
9. Xilkernel Process Model
• Units of execution within xilkernel: process
contexts
• Scheduling done at process context level
• POSIX threads API is primary user-visible
interface to process contexts
• Interfaces allow creating, destroying and
manipulating created application threads
(see Xilkernel API)
• Threads manipulated with thread identifiers
• Underlying process context is identified
with process identifier pid_t
10. Xilkernel scheduling model
• Xilkernel
– Priority-driven, preemptive scheduling
with time slicing (SCHED_PRIO)
– Simple Round-robin scheduling
(SCHED_RR)
• Cannot be changed on a per-thread
basis.
• Configured statically (at kernel
generation time)
11. Xilkernel scheduling model
• SCHED_RR
– Single ready queue
– Each process context executes for a
configured time slice before yielding
execution to the next process context in
the queue
12. Xilkernel scheduling model
• SCHED_PRIO
– As many ready queues as there are
priority levels
– Priority 0 → highest priority
– Higher values → lower priority
14. Xilkernel – Process Context States
• Each process context
– PROC_NEW
• A newly created process
– PROC_READY
• A process ready to execute
– PROC_RUN
• A process that is running
– PROC_WAIT
• A process that is blocked on a resource
– PROC_DELAY
• A process that is waiting for a timeout
– PROC_TIMED_WAIT
• A process that is blocked on a resource and has an
associated timeout
17. Xilkernel - Threading
• Thread (in xilkernel): a function that is
not necessarily processed linearly
• Threads are coded like functions, but
can work “in parallel”
• Threads
– Interacting with each other
– Pass data back and forth
18. Xilkernel - Threading
• At least one thread required to spawn
from the system at kernel start
• Main threads → void* without inputs
• “OS and Libraries”
– “config_pthread_support”
• static_pthread_table
19. Xilkernel - Threading
• Xilkernel
– 2 scheduling modes
• SCHED_PRIO
– Priority based scheduling
» Lower priority threads will always yield to
higher priority threads (lower priority number)
untill higher priority thread finishes or pthread-
joining is used
» If 2 threads with same priority → round-robin
based scheduling
• SCHED_RR
– Round-Robin based scheduling
» All threads must be processed at close-to the
same time. (“parallel”)
21. Xilkernel – Thread Management
• Xilkernel
– Basic POSIX threads API
• Thread creation and manipulation in
standard POSIX notation
• Threads identified by a unique thread
identifier
– type: pthread_t
22. Xilkernel - Semaphores
• Xilkernel supports Kernel allocated
POSIX semaphores
– Used for synchronization
• POSIX semaphores
– Counting semaphores (also below zero)
• Negative value: number of processes blocked
on the semaphore)
• Named semaphores
23. Xilkernel - Semaphores
• Mutex + extra functionality
– Can be given string names
– Contain “counting” information
• How many threads it is blocking
– More advanced waiting functions such as
timed-waiting
25. Xilkernel – Message Queues
• Xilkernel supports Kernel allocated X/
Open System Interface (XSI) message
queues
• XSI = optional interfaces under POSIX
• Message queues → IPC mechanism
• Depends on semaphore module and
dynamic buffer memory allocation
module
26. Xilkernel – Message Queues
• Extremely powerful feature
• Easy and safe means of transferring
data back and forth between multiple
processes
• Messaging is safe because the
functionality uses semaphores
internally
• Messages can take in custom structs
27. Xilkernel – Message Queues
• 4 functions are needed to setup, send
and receive messages between
threads
• Support for multiple messages in the
system
• msgget()
• msgctl()
• msgsnd()
• msgrcv()
28. Xilkernel – Shared Memory
• Xilkernel supports Kernel-allocated
XSI shared memory
– XSI: X/Open System Interface, an optional
interface under POSIX
• Shared memory
– Low-latency IPC mechanism
• Shared memory blocks required
during run-time must be identified
and specified during system
configuration
29. Xilkernel – Shared Memory
• Specification
– Buffer memory is allocated to each
shared memory region
• Shared Memory
– Not allocated dynamically at run-time
30. Xilkernel – Shared Memory
• Xilkernel supports Kernel-allocated
XSI shared memory
– X/Open System Interface
• Set of optional interfaces under POSIX
• Shared Memory
– Common, low-latency IPC mechanism
– Shared memory blocks
• Must be identified and specified during
system configuration
31. Xilkernel – Shared Memory
• From this specification
– Buffer memory allocated to each shared
memory region
• Shared memory is currently not
allocated dynamically at run-time
• Optional module can be configured in
or out during system specification
32. Xilkernel – Shared Memory
• int shmget()
• int shmctl()
• void* shmat()
• int shm_dt()
33. Xilkernel – Mutex Locks
• Xilkernel has support for Kernel allocated POSIX thread mutex locks
• This synchronization mechanism can be used alongside of the
pthread API
• Mutex lock types
– PTHREAD_MUTEX_DEFAULT
• Cannot be locked repeatedly by the owner. Attempts by a
thread to relock an already held mutex, or to lock a mutex
that was held by another thread when that thread
terminated result in a deadlock condition.
– PTHREAD_MUTEX_RECURSIVE
• A recursive mutex can be locked repeatedly by the owner.
The mutex doesn't become unlocked until the owner has
called pthread_mutex_unlock() for each successful lock
request that it has outstanding on the mutex.
34. Xilkernel - Mutex
• “Mutual exclusion lock”
– Very simple form of semaphore
• pthread_mutex_init()
• pthread_mutex_lock()
• pthread_mutex_unlock()
• pthread_mutexattr_init()
• pthread_mutexattr_settype()
35. Xilkernel – Dynamic Buffer Memory
Management
• Xilkernel provides a buffer memory
allocation scheme, can be used by
applications that need dynamic memory
allocation
• Alternatives for standard C memory
allocation routines like malloc() and free()
which are much slower and bigger, though
more powerful
• The allocation routines hand off pieces of
memory from a pool of memory that the
user passes to the buffer memory manager.
36. Xilkernel – Dynamic Buffer Memory
Management
• The buffer memory manager manages
the pool of memory. You can
dynamically create new pools of
memory.
• You can statically specify the different
memory blocks sizes and number of
such memory blocks required for your
applications
• This method of buffer management is
relatively simple, small and a fast way of
allocating memory.
37. Xilkernel – Dynamic Memory
• Used for allocating buffers of custom
sizes and widths
• bufcreate()
• bufdestroy()
• bufmalloc()
• buffree()
38. Xilkernel – Software Timers
• Xilkernel provides software timer
functionality, for time relating
processing.
– unsigned int xget_clock_ticks()
– time_t time(time_t *timer)
– unsigned sleep(unsigned int ms)
39. Xilkernel – Interrupt Handling
• Xilkernel abstracts primary interrupt
handling requirements from the user
application
• Even though the Kernel is functional
without any interrupts, it makes sense
for the system to be driven by a single
timer interrupt for scheduling.
40. Xilkernel – Interrupt Handling
• Kernel handles the main timer
interrupt, using it as the Kernel tick to
perform scheduling.
• The timer interrupt is initialized and
tied to the vectoring code during
system initialization.
• This Kernel pulse provides software
timer facilities and time-related
routines also.
41. Xilkernel – Interrupt Handling
• Additionally, Xilkernel can handle
multiple interrupts when connected
through an interrupt controller, and
works with the opb_intc interrupt
controller core.
43. Xilkernel – Exception Handling
• Xilkernel handles exceptions for the
MicroBlaze processor, threating them as
faulting conditions by the executing
processes/threads.
• Xilkernel kills the faulting process and
reports using a message to the console
(if verbose mode is on) as to the nature
of the exception.
• You cannot register your own handlers
for these exceptions and Xilkernel
handles them all natively.
44. Xilkernel – Interrupts in C
• Xilkernel abstracts the function calls
to the interrupt controller
• Peripherals must be tied to the
interrupt controller in hardware
– 1. “Software Platform Settings” under
“Interrupt Handlers” give desired interrupt a
handler name. The interrupt controller does
not require a handler unless the user would
like a special function call for any interrupt
that occurs
45. Xilkernel – Interrupts in C
– 2. In main code, initialize the interrupting
peripheral with it's API
– 3. Initialize the interrupting peripheral's
interrupt with it's API and start it running if
required (such as a timer)
– 4. use the xilkernel function:
“enable_interrupt()” - which takes in the
interrupt ID of the peripheral found in
“xparameters.h”. For the enable function
call, it is of type “int_id_t”
– 5. Have a function prepared with the handler
name
46. Xilkernel – Memory Protection
• Memory protection is an extremely
useful feature that can increase the
robustness, reliability, and fault
tolerance of your Xilkernel-based
application.
47. Xilkernel – Memory Protection
• Memory protection requires support
from the hardware.
• Xilkernel is designed to make use of
the MicroBlaze Memory Management
(Protection) Unit (MMU) features when
available. This allows you to build fail-
safe applications that each run within
the valid sandbox of the system, as
determined by the executable file and
available I/O devices.
48. Xilkernel – Memory Protection
• Note: Full virtual memory
management is not supported by
Xilkernel. Even when a full MMU is
available on MicroBlaze, only
transparent memory translations are
used, and there is no concept of
demand paging.
• Note: Xilkernel does not support the
same set of features using the MMU
on PowerPC processors.
49. Xilkernel – Hardware Requirements
• Scheduling and all the dependent
features require a periodic Kernel tick
and typically some kind of timer is
used.
• Xilkernel has been designed to be
able to work with either the Xilinx
fit_timer IP core or the opb_timer IP
core.
50. Xilkernel – Hardware Requirements
• Xilkernel has also been designed to
work in scenarios involving multiple-
interrupting peripherals.
• The opb_intc IP core is used to handle
the hardware interrupts and then feed
a single IRQ line from the controller to
the processor.
51. Xilkernel – Hardware Requirements
• By specifying the name of the
interruptcontroller peripheral in the
software platform configuration, you
would be getting Kernel awareness of
multiple interrupts. Xilkernel would
automatically initialize the hardware
cores, interrupt system, and the
second level of software handlers as a
part of its startup.
• You don't have to do this manually.
52. Xilkernel – Hardware Requirements
• Xilkernel handles non-cascaded
interrupt controllers; cascaded
interrupt controllers are not
supported.
53. Xilkernel – System Initialization
• The entry point for the Kernel is the
xilkernel_main( ) routine defined in
main.c.
• Any user initialization that must be
performed can be done before the call
to xilkernel_main( ). This includes any
system-wide features that might need
to be enabled before invoking
xilkernel_main( ).
54. Xilkernel – System Initialization
• These are typically machine-state
features such as cache enablement or
hardware exception enablement that
must be quot;always ONquot; even when
context switching between
applications.
• Make sure to set up such system
states before invoking xilkernel_main(
).
55. Xilkernel – System Initialization
• The first action that is performed
within xilkernel_init is kernel-specific
• hardware initialization.
– This includes
• registering the interrupt handlers and
configuring the system timer,
• as well as memory protection initialization.
Interrupts/exceptions are not enabled
• after completing hw_init( ). The
sys_init( ) routine is entered next.
56. Xilkernel – System Initialization
• This routine performs initialization of each module, such as
processes and threads, initializing in the following order:
– 1. Internal process context structures
– 2. Ready queues
– 3. pthread module
– 4. Semaphore module
– 5. Message queue module
– 6. Shared memory module
– 7. Memory allocation module
– 8. Software timers module
– 9. Idle task creation
– 10. Static pthread creation
• After these steps, interrupts, and exceptions are enabled, the
Kernel loops infinitely in the idle task, enabling the scheduler to
start scheduling processes.