In this paper, we show that cache partitioning does
not necessarily ensure predictable cache performance in modern
COTS multicore platforms that use non-blocking caches to exploit
memory-level-parallelism (MLP).
Through carefully designed experiments using three real COTS
multicore platforms (four distinct CPU architectures) and a cycleaccurate
full system simulator, we show that special hardware
registers in non-blocking caches, known as Miss Status Holding
Registers (MSHRs), which track the status of outstanding cachemisses,
can be a significant source of contention; we observe up
to 21X WCET increase in a real COTS multicore platform due
to MSHR contention.
We propose a hardware and system software (OS) collaborative
approach to efficiently eliminate MSHR contention for
multicore real-time systems. Our approach includes a low-cost
hardware extension that enables dynamic control of per-core
MLP by the OS. Using the hardware extension, the OS scheduler
then globally controls each core’s MLP in such a way that
eliminates MSHR contention and maximizes overall throughput
of the system.
We implement the hardware extension in a cycle-accurate fullsystem
simulator and the scheduler modification in Linux 3.14
kernel. We evaluate the effectiveness of our approach using a set
of synthetic and macro benchmarks. In a case study, we achieve
up to 19% WCET reduction (average: 13%) for a set of EEMBC
benchmarks compared to a baseline cache partitioning setup.
The document provides an overview of ARM processor architectures. It discusses ARM's range of RISC processor core designs including early processors like ARM7TDMI and ARM9TDMI. It covers the evolution of architectures like ARMv6, ARMv7, and ARMv7-M. It provides details on Cortex processor families like Cortex-A, Cortex-R, and Cortex-M. It describes features of various Cortex processors including pipeline stages, memory systems, and instruction sets. The document is intended to introduce the reader to ARM architectures and processor families.
A brief overview of linux scheduler, context switch , priorities and scheduling classes as well as new features. Also provides an overview of preemption models in linux and how to use each model. all the examples are taken from http://www.discoversdk.com
This document discusses Linux memory management. It outlines the buddy system, zone allocation, and slab allocator used by Linux to manage physical memory. It describes how pages are allocated and initialized at boot using the memory map. The slab allocator is used to optimize allocation of kernel objects and is implemented as caches of fixed-size slabs and objects. Per-CPU allocation improves performance by reducing locking and cache invalidations.
The document provides an overview of compute infrastructure, including:
- Physical computers contain components like CPUs, memory, ports, and connectivity.
- Early computers used vacuum tubes and punch cards. Transistors and ICs reduced size and cost.
- Common processor types include Intel/AMD x86, ARM, IBM POWER, Oracle SPARC.
- Early computer memory included magnetic cores and RAM chips replaced it. RAM types are SRAM and DRAM.
- The BIOS controls a computer from power on until the operating system loads.
Reduced instruction set computing, or RISC (pronounced 'risk', /ɹɪsk/), is a CPU design strategy based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction.
The document discusses cache coherence in multiprocessor systems. It describes the cache coherence problem that can arise when multiple processors have caches and can access shared memory. It then summarizes two primary hardware solutions: directory protocols which maintain information about which caches hold which memory lines; and snoopy cache protocols where cache controllers monitor bus traffic to maintain coherence without a directory. Finally it mentions a software-based solution relying on compiler analysis and operating system support.
Linux Memory Management with CMA (Contiguous Memory Allocator)Pankaj Suryawanshi
Fundamentals of Linux Memory Management and CMA (Contiguous Memory Allocator) In Linux.
Virtual Memory, Physical Memory, Swap Space, DMA, IOMMU, Paging, Segmentation, TLB, Hugepages, Ion google memory manager
This document discusses replacing external caching solutions with using the internal caching capabilities of ScyllaDB. It provides examples of companies that improved performance, reduced costs and complexity by moving from Redis or Elasticsearch with an external cache to using ScyllaDB's embedded cache instead. The document also outlines some of the advantages of ScyllaDB's cache like improved latency, coherency with the database and observability compared to external caching layers.
The document provides an overview of ARM processor architectures. It discusses ARM's range of RISC processor core designs including early processors like ARM7TDMI and ARM9TDMI. It covers the evolution of architectures like ARMv6, ARMv7, and ARMv7-M. It provides details on Cortex processor families like Cortex-A, Cortex-R, and Cortex-M. It describes features of various Cortex processors including pipeline stages, memory systems, and instruction sets. The document is intended to introduce the reader to ARM architectures and processor families.
A brief overview of linux scheduler, context switch , priorities and scheduling classes as well as new features. Also provides an overview of preemption models in linux and how to use each model. all the examples are taken from http://www.discoversdk.com
This document discusses Linux memory management. It outlines the buddy system, zone allocation, and slab allocator used by Linux to manage physical memory. It describes how pages are allocated and initialized at boot using the memory map. The slab allocator is used to optimize allocation of kernel objects and is implemented as caches of fixed-size slabs and objects. Per-CPU allocation improves performance by reducing locking and cache invalidations.
The document provides an overview of compute infrastructure, including:
- Physical computers contain components like CPUs, memory, ports, and connectivity.
- Early computers used vacuum tubes and punch cards. Transistors and ICs reduced size and cost.
- Common processor types include Intel/AMD x86, ARM, IBM POWER, Oracle SPARC.
- Early computer memory included magnetic cores and RAM chips replaced it. RAM types are SRAM and DRAM.
- The BIOS controls a computer from power on until the operating system loads.
Reduced instruction set computing, or RISC (pronounced 'risk', /ɹɪsk/), is a CPU design strategy based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction.
The document discusses cache coherence in multiprocessor systems. It describes the cache coherence problem that can arise when multiple processors have caches and can access shared memory. It then summarizes two primary hardware solutions: directory protocols which maintain information about which caches hold which memory lines; and snoopy cache protocols where cache controllers monitor bus traffic to maintain coherence without a directory. Finally it mentions a software-based solution relying on compiler analysis and operating system support.
Linux Memory Management with CMA (Contiguous Memory Allocator)Pankaj Suryawanshi
Fundamentals of Linux Memory Management and CMA (Contiguous Memory Allocator) In Linux.
Virtual Memory, Physical Memory, Swap Space, DMA, IOMMU, Paging, Segmentation, TLB, Hugepages, Ion google memory manager
This document discusses replacing external caching solutions with using the internal caching capabilities of ScyllaDB. It provides examples of companies that improved performance, reduced costs and complexity by moving from Redis or Elasticsearch with an external cache to using ScyllaDB's embedded cache instead. The document also outlines some of the advantages of ScyllaDB's cache like improved latency, coherency with the database and observability compared to external caching layers.
About a wide range of spectrum of Data Consistency models.
Created thanks to a lot of smart and generous people that shared their knowledge and insights into the subject. Thanks to you all !
Hope this can help you scratch the surface of the subject of consistency models too.
This document provides an introduction to distributed systems. It defines distributed systems in several ways, including as a collection of independent computers that appears as a single system to users. It discusses key characteristics like autonomy of components and transparency. The goals of distributed systems are also covered, such as remote accessibility, transparency, openness, and scalability. Examples of hardware organizations for distributed systems include multiprocessors, multicomputers, and heterogeneous systems.
The respective talk was held by Oleksandr Shevchenko (Senior Engineering Consultant, GlobalLogic) at GlobalLogic Lviv Embedded TechTalk #2 on May 23, 2018.
Oleksandr presentation is about features of software architecture, which provides parallel work of Linux and operating system real-time on different cores of a single processor. The talk is also about the Linux mechanism, which allows to connect the processor cores after the boot process has finished, the so-called "CPU Hotplug".
This document summarizes key concepts from Chapter 7 of the textbook Operating System Concepts by Silberschatz, Galvin and Gagne. It discusses deadlocks in computer systems, including their characterization and conditions for their occurrence. It also describes several approaches for handling deadlocks, such as prevention, avoidance, detection and recovery methods. The resource allocation graph and banker's algorithm are presented as techniques for deadlock avoidance when multiple instances of resources are present.
Receive side scaling (RSS) with eBPF in QEMU and virtio-netYan Vugenfirer
eBPF is a revolutionary technology that can run sandboxed programs in the Linux kernel without changing kernel source code or loading a kernel module. Receive side scaling (RSS) is the mechanism of packet steering for multi-queue NICs optimizing multiple CPU utilization. The first usage of eBPF in QEMU is the optimization of the RSS packet steering in virtio-net. During this session, Yan will provide the motives for the RSS optimization using eBPF, review the technical solution, describe integration with libvirt, and discuss future development and additional usages of eBPF in QEMU.
Using the new extended Berkley Packet Filter capabilities in Linux to the improve performance of auditing security relevant kernel events around network, file and process actions.
SOUG Day Oracle 21c New Security FeaturesStefan Oehrli
With the Innovation Release 21c Oracle has introduced one or the other security feature. These include small improvements that make DB operation more secure and easier. But also completely new concepts like DB Nest, which introduce a new approach for databases, how DB security can be implemented in multitenant.
Memory is organized in a hierarchy from fast but small CPU caches to larger but slower dynamic RAM (DRAM) and static RAM (SRAM), with the Linux kernel using zone allocation, buddy allocation, and slab allocation to manage physical memory and handle fragmentation issues across these storage and processing layers. Applications rely on standard library allocators like malloc while the kernel uses slab allocators like SLAB, SLUB, and SLOB to manage memory for internal data structures.
The document discusses developing network device drivers for embedded Linux. It covers key topics like socket buffers, network devices, communicating with network protocols and PHYs, buffer management, and differences between Ethernet and WiFi drivers. The outline lists these topics and others like throughput and considerations. Prerequisites include C skills, Linux knowledge, and an understanding of networking and embedded driver development.
- The document discusses Linux network stack monitoring and configuration. It begins with definitions of key concepts like RSS, RPS, RFS, LRO, GRO, DCA, XDP and BPF.
- It then provides an overview of how the network stack works from the hardware interrupts and driver level up through routing, TCP/IP and to the socket level.
- Monitoring tools like ethtool, ftrace and /proc/interrupts are described for viewing hardware statistics, software stack traces and interrupt information.
Linux PREEMPT_RT improves the preemptiveness of the Linux kernel by allowing preemption everywhere except when preemption is disabled or interrupts are disabled. This reduces latency from preemption, critical sections, and interrupts. However, non-deterministic external interrupt events and timing as well as interrupt collisions can still cause unpredictable latency. Tracing tools can help analyze latency but practical issues remain in fully guaranteeing hard real-time behavior.
Cache memory is located between the processor and main memory. It is smaller and faster than main memory. There are two types of cache memory policies - write-back and write-through. Mapping is a technique that maps CPU-generated memory addresses to cache lines. There are three types of mapping - direct, associative, and set associative. Direct mapping maps each main memory block to a single cache line using the formula: cache line number = main memory block number % number of cache lines. This can cause conflict misses.
Linux 4.x Tracing: Performance Analysis with bcc/BPFBrendan Gregg
Talk about bcc/eBPF for SCALE15x (2017) by Brendan Gregg. "BPF (Berkeley Packet Filter) has been enhanced in the Linux 4.x series and now powers a large collection of performance analysis and observability tools ready for you to use, included in the bcc (BPF Complier Collection) open source project. BPF nowadays can do system tracing, software defined networks, and kernel fast path: much more than just filtering packets! This talk will focus on the bcc/BPF tools for performance analysis, which make use of other built in Linux capabilities: dynamic tracing (kprobes and uprobes) and static tracing (tracepoints and USDT). There are now bcc tools for measuring latency distributions for file system I/O and run queue latency, printing details of storage device I/O and TCP retransmits, investigating blocked stack traces and memory leaks, and a whole lot more. These lead to performance wins large and small, especially when instrumenting areas that previously had zero visibility. Tracing superpowers have finally arrived, built in to Linux."
1) Design and Implementation of Multicore Processors
2) Coherence and Consistency
3) Power and Temperature
4) Interconnects
5) Multicore Caches
6) Security
7) Real world examples
The document discusses Linux networking architecture and covers several key topics in 3 paragraphs or less:
It first describes the basic structure and layers of the Linux networking stack including the network device interface, network layer protocols like IP, transport layer, and sockets. It then discusses how network packets are managed in Linux through the use of socket buffers and associated functions. The document also provides an overview of the data link layer and protocols like Ethernet, PPP, and how they are implemented in Linux.
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
This document summarizes the key characteristics and protocol of the I2C bus, which is a serial communication protocol used in embedded systems. It operates at speeds up to 5Mbps and uses just two bidirectional open-drain lines: a serial data line and a serial clock line. The I2C protocol uses a master-slave architecture, where the master device initiates data transfers by sending a start signal and addressing a slave device to read or write data. Transfers use 7 or 10-bit addressing and are acknowledged by the slave after each byte. The protocol supports multiple masters that must synchronize clocks and arbitrate access to the data line.
Tasklet vs work queues (Deferrable functions in linux)RajKumar Rampelli
Deferrable functions in linux is a mechanism to delay the execution of any piece of code later in the kernel context. Can be implemented using Tasklet and work queues
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore SystemsHeechul Yun
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core
can generate many parallel memory requests at a time. The processing of
these parallel requests in the DRAM controller greatly affects the memory
interference delay experienced by running tasks on the platform.
In this paper, we present a new parallelism-aware worst-case memory
interference delay analysis for COTS multicore systems. The analysis
considers a COTS processor that can generate multiple outstanding
requests and a COTS DRAM controller that has a separate read and write
request buffer, prioritizes reads over writes, and supports
out-of-order request processing. Focusing on LLC and DRAM bank
partitioned systems, our analysis computes worst-case upper bounds on
memory-interference delays, caused by competing memory requests.
We validate our analysis on a Gem5 full-system simulator modeling a
realistic COTS multicore platform, with a set of carefully designed
synthetic benchmarks as well as SPEC2006 benchmarks.
The evaluation results show that our analysis produces safe upper
bounds in all tested benchmarks, while the current state-of-the-art analysis significantly
under-estimates the delays.
Deterministic Memory Abstraction and Supporting Multicore System ArchitectureHeechul Yun
Presentation slides of the following paper at ECRTS'18.
Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." Euromicro Conference on Real-Time Systems (ECRTS), 2018
About a wide range of spectrum of Data Consistency models.
Created thanks to a lot of smart and generous people that shared their knowledge and insights into the subject. Thanks to you all !
Hope this can help you scratch the surface of the subject of consistency models too.
This document provides an introduction to distributed systems. It defines distributed systems in several ways, including as a collection of independent computers that appears as a single system to users. It discusses key characteristics like autonomy of components and transparency. The goals of distributed systems are also covered, such as remote accessibility, transparency, openness, and scalability. Examples of hardware organizations for distributed systems include multiprocessors, multicomputers, and heterogeneous systems.
The respective talk was held by Oleksandr Shevchenko (Senior Engineering Consultant, GlobalLogic) at GlobalLogic Lviv Embedded TechTalk #2 on May 23, 2018.
Oleksandr presentation is about features of software architecture, which provides parallel work of Linux and operating system real-time on different cores of a single processor. The talk is also about the Linux mechanism, which allows to connect the processor cores after the boot process has finished, the so-called "CPU Hotplug".
This document summarizes key concepts from Chapter 7 of the textbook Operating System Concepts by Silberschatz, Galvin and Gagne. It discusses deadlocks in computer systems, including their characterization and conditions for their occurrence. It also describes several approaches for handling deadlocks, such as prevention, avoidance, detection and recovery methods. The resource allocation graph and banker's algorithm are presented as techniques for deadlock avoidance when multiple instances of resources are present.
Receive side scaling (RSS) with eBPF in QEMU and virtio-netYan Vugenfirer
eBPF is a revolutionary technology that can run sandboxed programs in the Linux kernel without changing kernel source code or loading a kernel module. Receive side scaling (RSS) is the mechanism of packet steering for multi-queue NICs optimizing multiple CPU utilization. The first usage of eBPF in QEMU is the optimization of the RSS packet steering in virtio-net. During this session, Yan will provide the motives for the RSS optimization using eBPF, review the technical solution, describe integration with libvirt, and discuss future development and additional usages of eBPF in QEMU.
Using the new extended Berkley Packet Filter capabilities in Linux to the improve performance of auditing security relevant kernel events around network, file and process actions.
SOUG Day Oracle 21c New Security FeaturesStefan Oehrli
With the Innovation Release 21c Oracle has introduced one or the other security feature. These include small improvements that make DB operation more secure and easier. But also completely new concepts like DB Nest, which introduce a new approach for databases, how DB security can be implemented in multitenant.
Memory is organized in a hierarchy from fast but small CPU caches to larger but slower dynamic RAM (DRAM) and static RAM (SRAM), with the Linux kernel using zone allocation, buddy allocation, and slab allocation to manage physical memory and handle fragmentation issues across these storage and processing layers. Applications rely on standard library allocators like malloc while the kernel uses slab allocators like SLAB, SLUB, and SLOB to manage memory for internal data structures.
The document discusses developing network device drivers for embedded Linux. It covers key topics like socket buffers, network devices, communicating with network protocols and PHYs, buffer management, and differences between Ethernet and WiFi drivers. The outline lists these topics and others like throughput and considerations. Prerequisites include C skills, Linux knowledge, and an understanding of networking and embedded driver development.
- The document discusses Linux network stack monitoring and configuration. It begins with definitions of key concepts like RSS, RPS, RFS, LRO, GRO, DCA, XDP and BPF.
- It then provides an overview of how the network stack works from the hardware interrupts and driver level up through routing, TCP/IP and to the socket level.
- Monitoring tools like ethtool, ftrace and /proc/interrupts are described for viewing hardware statistics, software stack traces and interrupt information.
Linux PREEMPT_RT improves the preemptiveness of the Linux kernel by allowing preemption everywhere except when preemption is disabled or interrupts are disabled. This reduces latency from preemption, critical sections, and interrupts. However, non-deterministic external interrupt events and timing as well as interrupt collisions can still cause unpredictable latency. Tracing tools can help analyze latency but practical issues remain in fully guaranteeing hard real-time behavior.
Cache memory is located between the processor and main memory. It is smaller and faster than main memory. There are two types of cache memory policies - write-back and write-through. Mapping is a technique that maps CPU-generated memory addresses to cache lines. There are three types of mapping - direct, associative, and set associative. Direct mapping maps each main memory block to a single cache line using the formula: cache line number = main memory block number % number of cache lines. This can cause conflict misses.
Linux 4.x Tracing: Performance Analysis with bcc/BPFBrendan Gregg
Talk about bcc/eBPF for SCALE15x (2017) by Brendan Gregg. "BPF (Berkeley Packet Filter) has been enhanced in the Linux 4.x series and now powers a large collection of performance analysis and observability tools ready for you to use, included in the bcc (BPF Complier Collection) open source project. BPF nowadays can do system tracing, software defined networks, and kernel fast path: much more than just filtering packets! This talk will focus on the bcc/BPF tools for performance analysis, which make use of other built in Linux capabilities: dynamic tracing (kprobes and uprobes) and static tracing (tracepoints and USDT). There are now bcc tools for measuring latency distributions for file system I/O and run queue latency, printing details of storage device I/O and TCP retransmits, investigating blocked stack traces and memory leaks, and a whole lot more. These lead to performance wins large and small, especially when instrumenting areas that previously had zero visibility. Tracing superpowers have finally arrived, built in to Linux."
1) Design and Implementation of Multicore Processors
2) Coherence and Consistency
3) Power and Temperature
4) Interconnects
5) Multicore Caches
6) Security
7) Real world examples
The document discusses Linux networking architecture and covers several key topics in 3 paragraphs or less:
It first describes the basic structure and layers of the Linux networking stack including the network device interface, network layer protocols like IP, transport layer, and sockets. It then discusses how network packets are managed in Linux through the use of socket buffers and associated functions. The document also provides an overview of the data link layer and protocols like Ethernet, PPP, and how they are implemented in Linux.
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
This document summarizes the key characteristics and protocol of the I2C bus, which is a serial communication protocol used in embedded systems. It operates at speeds up to 5Mbps and uses just two bidirectional open-drain lines: a serial data line and a serial clock line. The I2C protocol uses a master-slave architecture, where the master device initiates data transfers by sending a start signal and addressing a slave device to read or write data. Transfers use 7 or 10-bit addressing and are acknowledged by the slave after each byte. The protocol supports multiple masters that must synchronize clocks and arbitrate access to the data line.
Tasklet vs work queues (Deferrable functions in linux)RajKumar Rampelli
Deferrable functions in linux is a mechanism to delay the execution of any piece of code later in the kernel context. Can be implemented using Tasklet and work queues
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore SystemsHeechul Yun
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core
can generate many parallel memory requests at a time. The processing of
these parallel requests in the DRAM controller greatly affects the memory
interference delay experienced by running tasks on the platform.
In this paper, we present a new parallelism-aware worst-case memory
interference delay analysis for COTS multicore systems. The analysis
considers a COTS processor that can generate multiple outstanding
requests and a COTS DRAM controller that has a separate read and write
request buffer, prioritizes reads over writes, and supports
out-of-order request processing. Focusing on LLC and DRAM bank
partitioned systems, our analysis computes worst-case upper bounds on
memory-interference delays, caused by competing memory requests.
We validate our analysis on a Gem5 full-system simulator modeling a
realistic COTS multicore platform, with a set of carefully designed
synthetic benchmarks as well as SPEC2006 benchmarks.
The evaluation results show that our analysis produces safe upper
bounds in all tested benchmarks, while the current state-of-the-art analysis significantly
under-estimates the delays.
Deterministic Memory Abstraction and Supporting Multicore System ArchitectureHeechul Yun
Presentation slides of the following paper at ECRTS'18.
Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." Euromicro Conference on Real-Time Systems (ECRTS), 2018
MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isola...Heechul Yun
This document describes MemGuard, an operating system mechanism for providing efficient per-core memory performance isolation on commercial off-the-shelf hardware. MemGuard uses memory bandwidth reservation to guarantee each core's minimum memory bandwidth. It then performs predictive bandwidth donation and on-demand reclaiming to redistribute excess bandwidth, improving overall utilization. Evaluation shows MemGuard isolates performance and eliminates over 50% slowdown of a foreground real-time task due to interference, while maximizing throughput via bandwidth sharing.
The document discusses various aspects of computer memory systems including main memory, cache memory, and memory mapping techniques. It provides details on:
1) Main memory stores program and data during execution and consists of addressable memory cells. Memory access time is the time for a memory operation while cycle time is the minimum delay between operations.
2) Memory units include RAM, ROM, PROM, EPROM, EEPROM and flash memory which have different characteristics like volatility and ability to be written.
3) Cache memory uses fast SRAM to improve performance by taking advantage of locality of reference where nearby memory accesses are common. Mapping techniques like direct, associative and set-associative mapping determine how
This document provides an overview of CPU caches, including definitions of key terms like SMP, NUMA, data locality, cache lines, and cache architectures. It discusses cache hierarchies, replacement strategies, write policies, inter-socket communication, and cache coherency protocols. Latency numbers for different levels of cache and memory are presented.
This document provides an overview of CPU caches, including definitions of key terms like SMP, NUMA, data locality, cache lines, and cache architectures. It discusses cache hierarchies, replacement strategies, write policies, inter-socket communication, and cache coherency protocols. Latency numbers for different levels of cache and memory are presented. The goal is to provide information to help improve application performance.
Caches are used in many layers of applications that we develop today, holding data inside or outside of your runtime environment, or even distributed across multiple platforms in data fabrics. However, considerable performance gains can often be realized by configuring the deployment platform/environment and coding your application to take advantage of the properties of CPU caches.
In this talk, we will explore what CPU caches are, how they work and how to measure your JVM-based application data usage to utilize them for maximum efficiency. We will discuss the future of CPU caches in a many-core world, as well as advancements that will soon arrive such as HP's Memristor.
This document discusses memory subsystems and hierarchy. It begins by describing the memory hierarchy which includes registers, main memory (RAM), and external memory. It then discusses different types of memory in terms of read/write capability, volatility, and erasure mechanisms. The document outlines cache organization and mapping techniques including direct mapping, set associative, and fully associative mapping. It provides examples of address mapping for each technique. The document also discusses RAM and ROM types as well as memory subsystem organization.
Memory access control in multiprocessor for real-time system with mixed criti...Heechul Yun
Proposed/implemented a memory bandwidth control mechanism on Linux kernel for Multi-core systems.
Described a timing analysis method based up on the proposed mechanism.
This presentation by Stanislav Donets (Lead Software Engineer, Consultant, GlobalLogic, Kharkiv) was delivered at GlobalLogic Kharkiv C++ Workshop #1 on September 14, 2019.
In this talk were covered:
- Graphics Processing Units: Architecture and Programming (theory).
- Scratch Example: Barnes Hut n-Body Algorithm (practice).
Conference materials: https://www.globallogic.com/ua/events/kharkiv-cpp-workshop/
Memory Hierarchy PPT of Computer Organization2022002857mbit
The document discusses memory hierarchy and cache design. It begins by listing sources used to create slides on this topic. It then provides definitions of key terms like cache hit, miss, hit time, and miss penalty. The document explains the principles of memory hierarchy, including exploiting locality of reference and implementing multiple memory levels with decreasing size but increasing speed. It discusses technologies like SRAM and DRAM that are commonly used for caches and main memory. The document also addresses four important questions in cache design: block placement, block identification, block replacement, and write strategy.
Erasing Belady's Limitations: In Search of Flash Cache Offline OptimalityYue Cheng
1) Unlike HDDs, flash SSDs erase data in large blocks and have a limited number of erasures before errors occur. When using SSDs as a cache for HDDs, the goal is to balance performance and endurance.
2) Existing flash caching algorithms aim to optimize read hit ratio (RHR) and endurance but it is unknown if they achieve the true offline optimal. The offline optimal maximizes RHR subject to an endurance limit.
3) The authors present a new container-optimized heuristic that maintains the optimal RHR while reducing erasures by up to 67% compared to existing algorithms. It outperforms prior work in balancing performance and endurance.
Multiprocessor systems can improve performance over single CPU systems by utilizing multiple processors that share memory and resources. However, scaling the number of processors is challenging due to bottlenecks like shared bus bandwidth. Various multiprocessor architectures aim to improve scalability, including cache consistency protocols, crossbar switches, and non-uniform memory access designs. Effective parallelization of workloads and careful management of shared data is also important. Implementing an operating system for multiprocessors presents challenges like concurrency in the kernel and efficient synchronization between processors.
Apache Spark on Supercomputers: A Tale of the Storage Hierarchy with Costin I...Databricks
In this session, the speakers will discuss their experiences porting Apache Spark to the Cray XC family of supercomputers. One scalability bottleneck is in handling the global file system present in all large-scale HPC installations. Using two techniques (file open pooling, and mounting the Spark file hierarchy in a specific manner), they were able to improve scalability from O(100) cores to O(10,000) cores. This is the first result at such a large scale on HPC systems, and it had a transformative impact on research, enabling their colleagues to run on 50,000 cores.
With this baseline performance fixed, they will then discuss the impact of the storage hierarchy and of the network on Spark performance. They will contrast a Cray system with two levels of storage with a “data intensive” system with fast local SSDs. The Cray contains a back-end global file system and a mid-tier fast SSD storage. One conclusion is that local SSDs are not needed for good performance on a very broad workload, including spark-perf, TeraSort, genomics, etc.
They will also provide a detailed analysis of the impact of latency of file and network I/O operations on Spark scalability. This analysis is very useful to both system procurements and Spark core developers. By examining the mean/median value in conjunction with variability, one can infer the expected scalability on a given system. For example, the Cray mid-tier storage has been marketed as the magic bullet for data intensive applications. Initially, it did improve scalability and end-to-end performance. After understanding and eliminating variability in I/O operations, they were able to outperform any configurations involving mid-tier storage by using the back-end file system directly. They will also discuss the impact of network performance and contrast results on the Cray Aries HPC network with results on InfiniBand.
Apache Spark on Supercomputers: A Tale of the Storage Hierarchy with Costin I...Databricks
In this session, the speakers will discuss their experiences porting Apache Spark to the Cray XC family of supercomputers. One scalability bottleneck is in handling the global file system present in all large-scale HPC installations. Using two techniques (file open pooling, and mounting the Spark file hierarchy in a specific manner), they were able to improve scalability from O(100) cores to O(10,000) cores. This is the first result at such a large scale on HPC systems, and it had a transformative impact on research, enabling their colleagues to run on 50,000 cores.
With this baseline performance fixed, they will then discuss the impact of the storage hierarchy and of the network on Spark performance. They will contrast a Cray system with two levels of storage with a “data intensive” system with fast local SSDs. The Cray contains a back-end global file system and a mid-tier fast SSD storage. One conclusion is that local SSDs are not needed for good performance on a very broad workload, including spark-perf, TeraSort, genomics, etc.
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Taming Non-blocking Caches to Improve Isolation in Multicore Real-Time Systems
1. Taming Non-blocking Caches to Improve
Isolation in Multicore Real-Time Systems
Prathap Kumar Valsan, Heechul Yun, Farzad Farshchi
University of Kansas
1
3. Time Predictability Challenge
3
Core1 Core2 Core3 Core4
Memory Controller (MC)
Shared Cache
• Shared hardware resource contention can cause
significant interference delays
• Shared cache is a major shared resource
DRAM
Task 1 Task 2 Task 3 Task 4
4. Cache Partitioning
• Can be done in either software or hardware
– Software: page coloring
– Hardware: way partitioning
• Eliminate unwanted cache-line evictions
• Common assumption
– cache partitioning performance isolation
• If working-set fits in the cache partition
• Not necessarily true on out-of-order cores using
non-blocking caches
4
5. Outline
• Evaluate the isolation effect of cache partitioning
– On four real COTS multicore architectures
– Observed up to 21X slowdown of a task running on a
dedicated core accessing a dedicated cache partition
• Understand the source of contention
– Using a cycle-accurate full system simulator
• Propose an OS/architecture collaborative solution
– For better cache performance isolation
5
6. Memory-Level Parallelism (MLP)
• Broadly defined as the number of concurrent
memory requests that a given architecture
can handle at a time
6
7. Non-blocking Cache(*)
• Can serve cache hits under multiple cache misses
– Essential for an out-of-order core and any multicore
• Miss-Status-Holding Registers (MSHRs)
– On a miss, allocate a MSHR entry to track the req.
– On receiving the data, clear the MSHR entry
7
cpu cpu
miss hit miss
Miss penalty
Miss penalty
stall only when
result is needed
Multiple outstanding misses
(*) D. Kroft. “Lockup-free instruction fetch/prefetch cache organization,” ISCA’81
8. Non-blocking Cache
• #of cache MSHRs memory-level parallelism
(MLP) of the cache
• What happens if all MSHRs are occupied?
– The cache is locked up
– Subsequent accesses---including cache hits---to
the cache stall
– We will see the impact of this in later experiments
8
10. Identified MLP
• Local MLP
– MLP of a core-private cache
• Global MLP
– MLP of the shared cache (and DRAM)
10
(See paper for our experimental identification method)
Cortex-A7 Cortex-A9 Cortex-A15 Nehalem
Local MLP 1 4 6 10
Global MLP 4 4 11 16
11. Cache Interference Experiments
• Measure the performance of the ‘subject’
– (1) alone, (2) with co-runners
– LLC is partitioned (equal partition) using PALLOC (*)
• Q: Does cache partitioning provide isolation?
11
DRAM
LLC
Core1 Core2 Core3 Core4
subject co-runner(s)
(*) Heechul Yun, Renato Mancuso, Zheng-Pei Wu, Rodolfo Pellizzoni. “PALLOC: DRAM Bank-Aware Mem
ory Allocator for Performance Isolation on Multicore Platforms.” RTAS’14
12. IsolBench: Synthetic Workloads
• Latency
– A linked-list traversal, data dependency, one outstanding miss
• Bandwidth
– An array reads or writes, no data dependency, multiple misses
• Subject benchmarks: LLC partition fitting
12
Working-set size: (LLC) < ¼ LLC cache-hits, (DRAM) > 2X LLC cache misses
13. Latency(LLC) vs. BwRead(DRAM)
• No interference on Cortex-A7 and Nehalem
• On Cortex-A15, Latency(LLC) suffers 3.8X slowdown
– despite partitioned LLC
13
14. BwRead(LLC) vs. BwRead(DRAM)
• Up to 10.6X slowdown on Cortex-A15
• Cache partitioning != performance isolation
– On all tested out-of-order cores (A9, A15, Nehalem)
14
15. BwRead(LLC) vs. BwWrite(DRAM)
• Up to 21X slowdown on Cortex-A15
• Writes generally cause more slowdowns
– Due to write-backs
15
17. MSHR Contention
• Shortage of cache MSHRs lock up the cache
• LLC MSHRs are shared resources
– 4cores x L1 cache MSHRs > LLC MSHRs
17
Cortex-A7 Cortex-A9 Cortex-A15 Nehalem
Local MLP 1 4 6 10
Global MLP 4 4 11 16
(See paper for our experimental identification method)
18. Outline
• Evaluate the isolation effect of cache
partitioning
• Understand the source of contention
– Effect of LLC MSHRs
– Effect of L1 MSHRs
• Propose an OS/architecture collaborative
solution
18
20. Effect of LLC (Shared) MSHRs
• Increasing LLC MSHRs eliminates the MSHR contention
• Issue: scalable?
– MSHRs are highly associative (must be accessed in parallel)
20
L1:6/LLC:12 MSHRs L1:6/LLC:24 MSHRs
21. Effect of L1 (Private) MSHRs
• Reducing L1 MSHRs can eliminate contention
• Issue: single thread performance. How much?
– It depends. L1 MSHRs are often underutilized
– EEMBC: low, SD-VBS: medium, SPEC2006: high
21
EEMBC, SD-VBS IsolBench,SPEC2006
22. Outline
• Evaluate the isolation effect of cache
partitioning
• Understand the source of contention
• Propose an OS/architecture collaborative
solution
22
23. OS Controlled MSHR Partitioning
23
• Add two registers in each core’s L1 cache
– TargetCount: max. MSHRs (set by OS)
– ValidCount: used MSHRs (set by HW)
• OS can control each core’s MLP
– By adjusting the core’s TargetCount register
Block Addr.Valid Issue Target Info.
Block Addr.Valid Issue Target Info.
Block Addr.Valid Issue Target Info.
MSHR 1
MSHR 2
MSHR n
TargetCount ValidCount
Last Level Cache (LLC)
Core
1
Core
2
Core
3
Core
4
MSHRs
MSHRs MSHRs MSHRs MSHRs
24. OS Scheduler Design
• Partition LLC MSHRs by enforcing
• When RT tasks are scheduled
– RT tasks: reserve MSHRs
– Non-RT tasks: share remaining MSHRs
• Implemented in Linux kernel
– prepare_task_switch() at kernel/sched/core.c
24
25. Case Study
• 4 RT tasks (EEMBC)
– One RT per core
– Reserve 2 MSHRs
– P: 20,30,40,60ms
– C: ~8ms
• 4 NRT tasks
– One NRT per core
– Run on slack
• Up to 20% WCET reduction
– Compared to cache partition only
25
26. Conclusion
• Evaluated the effect of cache partitioning on four real COTS
multicore architectures and a full system simulator
• Found cache partitioning does not ensure cache (hit)
performance isolation due to MSHR contention
• Proposed low-cost architecture extension and OS scheduler
support to eliminate MSHR contention
• Availability
– https://github.com/CSL-KU/IsolBench
– Synthetic benchmarks (IsolBench),test scripts, kernel patches
26
27. Exp3: BwRead(LLC) vs. BwRead(LLC)
• Cache bandwidth contention is not the main source
– Higher cache-bandwidth co-runners cause less slowdowns
27
28. EEMBC, SD-VBS Workload
• Subject
– Subset of EEMBC, SD-VBS
– High L2 hit, Low L2 miss
• Co-runners
– BwWrite(DRAM): High L2 miss, write-intensive
28
Editor's Notes
This talk is about improving isolation in modern multicore real-time systems focusing on shared cache.
High-performance multicore processors are increasingly demanded in many modern real-time systems to satisfy the ever increasing performance need while reducing size, weight, and power consumption.
Unfortunately, it is well know that providing timing predictability is very difficult in multicore processors due to contention in shared hardware resources. In this work, we focus on shared cache.
Cache partitioning is a well known technique to improve isolation for real-time systems. And it can be done either in software (by the OS) or in hardware. Either way, the goal of partitioning is to eliminate the unwanted cache-line evictions by providing isolated space per core/task.
Most literature equate cache partitioning and cache performance isolation. However, as we will show in this work, partitioning cache doesn’t necessarily provide performance isolation in modern high-performance multicore architectures.
This talk is composed of three parts. First, we evaluate the isolation effect cache partitioning on four real COTS multicore architectures. Surprisingly, we observe up to 21X slowdown of a task running on a dedicated core, accessing dedicated cache partition, and almost all memory accesses are cache hits.
We then further investigate and better understand the source of the contention using a cycle accurate full system simulator.
Finally, based on the understanding, we propose an OS and architecture collaborative solution to to provide true cache performance isolation.
Before we begin, let me briefly introduce essential background on non-blocking caches. A non-blocking cache can continue to serve cache-hit requests under multiple cache misses. Supporting multiple outstanding misses is important to leverage memory-level parallelism. And it is especially important for out-of-order cores, but in-order multicore also can benefit from using non-blocking shared caches.
In a non-blocking cache, there are special hardware registers known as miss-status-holing registers (MSHRs). When a cache miss occurs, the cache controller allocates a MSHR entry to track the outgoing cache-miss and it is cleared when the data is delivered from the lower-level memory hierarch,
The number of MSHRs essentially determines the parallelism of the cache. Now, because MSHRs are limited and getting the data from DRAM could take 100s of cpu cycles, it is possible that MSRHs of a cache are fully occupied with outstanding misses. If that happens, the cache lock-up and all the subsequent accesses to the cache will be stalled.
For experiments, we use four COTS multicore architectures. One in-order and three out-of-order architectuers.
On the platforms, we perform a set of cache-interference experiments. The basic setup is as follows. We ran a subject benchmark on one core, and we increase the number of co-runners on the other cores. I would like to stress that the LLC is partitioned on a per-core basis. So, what we would like to see is whether cache portioning provide cache performance isolation.
First, we use a benchmark suite called IsolBench that consists of two synthetic benchmarks latency and bandwidth. The latency benchmark is a simple linked-list traversal program. Due to data dependency, only one outstanding miss can be generated at a time. The bandwidth benchmark is a simple array access program. As there’s no data dependency, multiple concurrent accesses can be made in an out-of-order core. We created 6 workloads with varying their working-set sizes. Here, LLC denotes less than the given cache partiion while (DRAM) denotes twice size of the the LLC. In all workloads, the subject benchmarks always fit in their cache partitions. In other words, accesses are cache hits. So, ideally, cache partitioning should provide performance isolation regardless of the co-runners.
We also used real benchmarks as subjects and get the similar results. That is isolation is provided in in-order cores but not so in out-of-order cores
We attribute this to the MSHR contention problem. This table shows the experimentally obtained core local and global memory-level parallelism of the tested platforms. Detailed methods to obtain MLP is in paper. These numbers were also validated from the manuals of the processors. What this table suggests is that the MSHRs in the LLCs are smaller than the sum of L1 MSHRs on the tested out-of-order cores. As I mentioned before, then the shortage of the LLC MSHRs can lock-up the LLC, even if the cache space is partitioned.
Next, we validate the MSHR contention problem using a cycle-accurate full system simulator. We also perform a set of sensitive analysis to better understand the effects of MSHRs in the local and shared caches.
At first, we suspected that this may be because of shared bus that connects the LLC and the cores. But we found that it was not the case from next experiment. In this experiment, we chaged the corunners’ working-set sizes to fit in their cache partitions. Because now that co-runners’ memory accesses are also cache hits, the cache bandwidth demand, and therefore the shared bus contention would have been increased. Yet, the slowdown becomes much smaller than the previous experiment where cache bandwidth usages were much lower.