This paper shows the details for implementing an interface between the programming language R and programmable fabric of a Xilinx Zynq FPGA on a zedboard.

1. vincent@cteq.eu https://www.linkedin.com/in/vincentclaes/ 1
Abstract—R is a programming language for statistical
computing. It has many built in functions for statistical
calculations of large datasets and even more available libraries to
expand this functionality. R is however fundamentally single
threaded. As the size of the used datasets increases, so does the
processing time. This limits the use of R in real-time applications
with large amounts of data where statistical analysis is necessary.
By offloading intensive calculations to an FPGA with massive
parallel processing power these calculations can be sped up to
make R valid for real-time processing. This paper proposes a
simple way to send data from an application in R to the digital
logic in an FPGA and back. In this way applications like sensor
fusion systems, machine learning algorithms for “Internet-of-
things” applications can be realized in the future on this Xilinx
Zynq embedded systems platform. In this way intelligent IoT
Gateways could be realized.
Index Terms— R-project, R, FPGA, Statistical computing,
hardware acceleration, Xillybus, Xilinx, Zynq, zedboard, machine
learning, sensor fusion
I. INTRODUCTION
He last few years we have seen a massive increase in
interest in using FPGAs (Field Programmable Gate Arrays)
to offload difficult calculation from processors. By
leveraging custom digital logic with its parallel potential
processes, which are normally run solely on a processor, can be
sped up and power consumption decreased. At first sight,
combining software with digital logic seems like a daunting
task. Besides software design and digital logic design an
interface has to be created between the two. For these reasons
it is often avoided unless absolutely necessary. Fortunately
there exist tools to simplify this design process, especially the
interface between the application software and digital logic. To
illustrate this, this paper provides a solution to interface an
application written on R and running on a Linux host with
digital logic on an FPGA. With this interface hardware
acceleration for intensive calculations can be implemented on
the FPGA while the ease of use and native support for statistical
computing of R is retained.
II. TOOLS AND SOFTWARE
A zedboard was used as development board. It is a board with
T. Nulens is a student at Hasselt University, Faculty of Engineering
Technology, Diepenbeek, Belgium. E-mail: tom.nulens@student.uhasselt.be.
a Xilinx Zynq system-on-chip and various inputs and outputs
like USB, VGA and much more. The Zynq system-on-chip
consists of a 32bit ARM dual core processor and a large amount
of programmable logic.
Figure 1 Top and bottom view of the zedboard
The application software runs on the processor and
communicates with the programmable logic as required. A
special distribution of Ubuntu, named Xillinux, is installed on
the processor. Xillinux is a version of Ubuntu LTS 12.04 for
ARM with Xillybus drivers preinstalled. The operating system
runs from a SD card which acts as hard drive for the zedboard.
Finally, R version 3.1.2 was installed. Since Xillybus is already
supported on this device, it’s the obvious choice to use as
interface between the processor and digital logic. Xillybus takes
care of both the digital logic implementation and the software
drivers for the interface. It also works with both AXI (Advanced
eXtensible Interface) and PCIe (Peripheral Component
Interconnect Express) which makes it possible to transfer the
application on the Zynq system-on-chip to a full desktop
without worrying about those interfaces.
III. XILLYBUS
Xillybus is a combination of an IP core for the FPGA as well as
a driver for the operating system on the processor. Together it
allows a simple interface between the digital logic and the
application software. The IP core implements the digital logic
required to send and receive data from the processor with First
In First Out shift (FIFO) registers. It provides the signals to
drive FIFO registers, signals like clock and write enable. These
signals must then be used to drive a user-defined FIFO in the
implementation. The Xillybus IP core then connects to a PCIe
V. Claes is the owner of cteq.eu vincent@cteq.eu
https://www.linkedin.com/in/vincentclaes/
Implementing an interface in R to communicate
with Programmable Fabric in a Xilinx ZYNQ
FPGA
Vincent Claes, Tom Nulens [Project realized in 2015]
T

2. vincent@cteq.eu https://www.linkedin.com/in/vincentclaes/ 2
interface IP core or AXI (Advanced eXtensible Interface) IP
core, depending on the platform. In the Zynq chip, AXI is used
to connect the digital logic to the processor. The IP core is
generated at the IP factory web interface on the website of
Xillybus. Specifications such as bandwidth, data width and data
direction are defined here. Afterwards the IP core is generated
and available for download. The bandwidth on an AXI interface
is limited to 200 Mbytes/s.
Figure 2 FPGA block diagram with the Xillybus IP core and a PCIe
interface
On the processor side the Xillybus driver allows read and write
operations through a standard input/output file-interface. A data
connection is opened between the application software and
digital logic by simply opening a file defined by the Xillybus
driver and writing to or reading from that file.
Figure 3 Processor host interface block diagram
IV. INTERFACE BETWEEN R AND XILLYBUS
A. Problems with interfacing R with Xillybus
In the previous paragraph I noted that to write to or read from
the FPGA a standard file IO system is everything that is
required. Although R has this functionality, reading or writing
in native R is not very efficient for real-time applications for
two reasons: First, an R application is single threaded. This
means that when transferring data back and forth between the
processor and FPGA, no other calculation can be performed by
the processor. With large datasets a significant amount of time
would be lost due to this data transferring. By doing the reading
and writing in background threads the host application can
continue with different calculations regardless of what is
happening in the digital logic. There are some solutions for
parallelism in R, they are however aimed at dividing
calculations over multiple cores instead of doing different tasks
concurrently. Second, as a high level programming language,
datatype manipulation is less transparent than it is in languages
like C. Depending on the digital logic you have designed, the
interface will expect anything ranging from 32bit doubles to
8bit unsigned integers. For this reason it is advantageous to use
a language with explicit datatypes.
B. Proposed solution
By using the R library Rcpp, C++ functions and classes can be
called from R. Rcpp provides a C++ header file with the
definition for an R object. This object along with a short
wrapper allows Rcpp to compile custom C++ classes and
functions that can directly take R objects as argument and return
them too. C++ can then be used to prepare data from R to write
to the FPGA or to read data from the FPGA before returning it
to R. By combining this with the C++ library thread.h read and
write functionality can be given separate threads from the main
R thread. The Xillybus programming guide proposes the
following diagram for an implementation of hardware
acceleration:
Figure 4 Host-FPGA interface with Thread A as writer and Thread B
as reader. Main thread not pictured
In the main thread two threads are started, one to write data to
the FPGA and one to read the calculated results. These two
threads run continuously in the background while different
calculations can still be performed in the main thread. A
continues data flow is possible in this implementation provided
enough data is fed into the write thread to make use of the full
bandwidth. The write thread takes care of the translation of the
R objects to the datatypes the digital logic expects while the
read thread takes care of the reverse.
C. Implementation
First use the Xillybus IP factory to generate an IP core with
separate downstream and upstream device files and implement
this IP core in the FPGA design.
Figure 5 Configuration of an upstream and downstream device file in
the Xillybus IP factory
Afterwards a regular C++ class can be written to open those two
device files to read and write from separate threads. Make sure
to use the R objects defined by the Rcpp header file as
arguments and return values for the methods in this class. The
R wrapper is defined separately from the class definition but it
is placed in the same source file.

3. vincent@cteq.eu https://www.linkedin.com/in/vincentclaes/ 3
Figure 6 Example of the R wrapper for a C++ class called ‘Manager’
In the wrapper definition the chosen class is given along with
the names for all the exposed methods as well as function
pointers to the corresponding methods in their C++ class. This
source file is then ready to be compiled through Rcpp with the
command: sourceCpp(“/path/class.cpp”). At that point the class
is ready to be used in R. The following R script illustrates the
implementation of the interface.
Figure 7 R script with FPGA interface. Green are comments, red are
the outputs
In the above script a loopback is implemented in the FPGA. The
Class Manager was written in C++. The object u is an instance
of Manager.
V. CONCLUSION
An interface between an R application and an FPGA has been
made. The processor and FPGA reside on the same system-on-
chip and are connected by AXI. By using Xillybus the
complexity on the software side that comes from AXI is
completely removed. The Xillybus driver also works regardless
of whether the interface is AXI or PCIe which means that the
whole application can be moved to a desktop computer with an
FPGA board connected on a PCIe slot in case this becomes
desirable. On the FPGA side the IP core governs the interface
and requires only a read and write FIFO in the user logic. The
complexity of AXI or PCIe on the FPGA is reduced to
connecting the right signals from the Xillybus IP core to the
fitting Xilinx or Altera IP core. This interface is therefore ideal
for rapid prototyping.
VI. ACKNOWLEDGEMENT
This project was realized for cteq.eu [http://www.cteq.eu] with
support from Hasselt University. I would like to thank V. Claes
for technical support.
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