16-bit ALU(Arithmetic Logic Unit) using 130nm process. Software tools that were used are Cadence, HSpice, Design Vision, Siliconsmart, Waveview, Encounter and Primetime
An Arithmetic Logic Unit (ALU) is a functional block of any
processor. It is used to perform arithmetical and logical
operations. ALU’s are designed to perform integer based
operations. In this module, we have designed an ALU which
performs certain specific operations on 32 bit numbers.
The arithmetic operations performed are: Addition, subtraction
and multiplication. The logical operations performed are: AND,
OR, XNOR, left shift and right shift.
The behavioral Verilog code and testbench were simulated using
MODELSIM to verify the functionality.
The individual gates (INVERTER, NAND2, NOR2, XOR2, OAI3222,
AOI22, MUX2:1) which constituted to the cell library were laid out
in CADENCE. The DRC and LVS run were successfully completed
to ensure usage. These individual layouts were combined and the
combined DRC was run without any errors.
The D flip flop (DFF) was laid out and the static timing analysis
were done using Waveform viewer and it’s functionality was
verified and the D flip flop times were calculated.
By putting together these cells which were designed, the ALU was
developed and the outputs were obtained.
Vhdl code and project report of arithmetic and logic unitNikhil Sahu
The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 8 bit ALU which accepts two 8 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations that we dealt with, are arithmetical, logical and relational. Arithmetic operations include arithmetic addition, subtraction, multiplication and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and result in output logically operated. The operations like the greater than, less than, equal to, exponential etc are also included. To implement ALU, the coding was written in VHDL . The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Synthesis translates VHDL code into netlist (a textual description). Thereafter, the simulation was done to verify the synthesized code.
An Arithmetic Logic Unit (ALU) is a functional block of any
processor. It is used to perform arithmetical and logical
operations. ALU’s are designed to perform integer based
operations. In this module, we have designed an ALU which
performs certain specific operations on 32 bit numbers.
The arithmetic operations performed are: Addition, subtraction
and multiplication. The logical operations performed are: AND,
OR, XNOR, left shift and right shift.
The behavioral Verilog code and testbench were simulated using
MODELSIM to verify the functionality.
The individual gates (INVERTER, NAND2, NOR2, XOR2, OAI3222,
AOI22, MUX2:1) which constituted to the cell library were laid out
in CADENCE. The DRC and LVS run were successfully completed
to ensure usage. These individual layouts were combined and the
combined DRC was run without any errors.
The D flip flop (DFF) was laid out and the static timing analysis
were done using Waveform viewer and it’s functionality was
verified and the D flip flop times were calculated.
By putting together these cells which were designed, the ALU was
developed and the outputs were obtained.
Vhdl code and project report of arithmetic and logic unitNikhil Sahu
The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 8 bit ALU which accepts two 8 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations that we dealt with, are arithmetical, logical and relational. Arithmetic operations include arithmetic addition, subtraction, multiplication and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and result in output logically operated. The operations like the greater than, less than, equal to, exponential etc are also included. To implement ALU, the coding was written in VHDL . The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Synthesis translates VHDL code into netlist (a textual description). Thereafter, the simulation was done to verify the synthesized code.
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Rahul Borthakur
The main objective of this project was to design and verify different operations of Arithmetic and Logical Unit (ALU). To implement ALU, the coding was written in VHDL (VHSIC Hardware Description Language) and verified in ModelSim. The device was configured and using FPGA (Field-programmable gate array) verification, debugging was done.
8 Bit ALU is a combinational circuit which accepts two 8-bit numbers gives result.It is designed using the Verilog HDL code which is more useful for bachelor as well as masters engineering students.
Speed checker on highway using 8051 micro controller and IR sensors. Here IR sensor sense the speed of the vehicle and and controller display the speed on Liquid Crystal Display,
Verilog Code for 16bit RISC Processor, with ALU, Program Counter, Instruction Memory, Data Memory and Control Unit full codes
Visit www.Hellocodings.com
AUTOMATIC ROOM LIGHTING SYSTEM is very effective project on a large scale because of the conservation of energy and electricity.
I think that it should have large scale production by multinational companies like TATA etc.
Thankyou for the visit!.
Introduction to Verilog HDL. This class notes present basic HDL structures, data types, operators, and expressions in Verilog. It also describes three typical modeling style for HDL design; behavioral, dataflow, and structural.
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Rahul Borthakur
The main objective of this project was to design and verify different operations of Arithmetic and Logical Unit (ALU). To implement ALU, the coding was written in VHDL (VHSIC Hardware Description Language) and verified in ModelSim. The device was configured and using FPGA (Field-programmable gate array) verification, debugging was done.
8 Bit ALU is a combinational circuit which accepts two 8-bit numbers gives result.It is designed using the Verilog HDL code which is more useful for bachelor as well as masters engineering students.
Speed checker on highway using 8051 micro controller and IR sensors. Here IR sensor sense the speed of the vehicle and and controller display the speed on Liquid Crystal Display,
Verilog Code for 16bit RISC Processor, with ALU, Program Counter, Instruction Memory, Data Memory and Control Unit full codes
Visit www.Hellocodings.com
AUTOMATIC ROOM LIGHTING SYSTEM is very effective project on a large scale because of the conservation of energy and electricity.
I think that it should have large scale production by multinational companies like TATA etc.
Thankyou for the visit!.
Introduction to Verilog HDL. This class notes present basic HDL structures, data types, operators, and expressions in Verilog. It also describes three typical modeling style for HDL design; behavioral, dataflow, and structural.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
Behavioral Design and Synthesis of 64 BIT ALU using Xilinx ISEIOSR Journals
Abstract: This paper presents the behavioral Design and synthesis of a 64 bit ALU. 64 bit ALU is basically a multiplexer that operates mainly 16 operations as per select line Bit-permutation. Flags are other important indicators used for specific purpose e.g. if Sign Flag is HIGH then the output of ALU must be a negative number. CLR can reset the output of ALU.
Keywords: Flags, CLR, 64 Bit ALU, VHDL.
Abstract: In this paper VHDL implementation of 64-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 9.1 and targeted for Spartan device. ALU was designed to perform arithmetic operation and logical operations such as addition , subtraction using 64-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1’scomplement, rotate operations and compare. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 64-bit fast adder with 2’s complement circuit to perform subtraction and logic gates to perform logical operation. The maximum propagation delay is 13.588ns and power dissipation is 38mW. Keywords: ALU, Fast Adder, XILINX, VHDL
Hello everyone! I am thrilled to present my latest portfolio on LinkedIn, marking the culmination of my architectural journey thus far. Over the span of five years, I've been fortunate to acquire a wealth of knowledge under the guidance of esteemed professors and industry mentors. From rigorous academic pursuits to practical engagements, each experience has contributed to my growth and refinement as an architecture student. This portfolio not only showcases my projects but also underscores my attention to detail and to innovative architecture as a profession.
Between Filth and Fortune- Urban Cattle Foraging Realities by Devi S Nair, An...Mansi Shah
This study examines cattle rearing in urban and rural settings, focusing on milk production and consumption. By exploring a case in Ahmedabad, it highlights the challenges and processes in dairy farming across different environments, emphasising the need for sustainable practices and the essential role of milk in daily consumption.
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Book Formatting: Quality Control Checks for DesignersConfidence Ago
This presentation was made to help designers who work in publishing houses or format books for printing ensure quality.
Quality control is vital to every industry. This is why every department in a company need create a method they use in ensuring quality. This, perhaps, will not only improve the quality of products and bring errors to the barest minimum, but take it to a near perfect finish.
It is beyond a moot point that a good book will somewhat be judged by its cover, but the content of the book remains king. No matter how beautiful the cover, if the quality of writing or presentation is off, that will be a reason for readers not to come back to the book or recommend it.
So, this presentation points designers to some important things that may be missed by an editor that they could eventually discover and call the attention of the editor.
1. The University of Texas at Dallas
EECT 6325- VLSI DESIGN
Fall 2018
16-bit ALU (Arithmetic Logic Unit)
by
Vignesh Ganesan – VXG170004
Jayashree Jayabalan – JXJ180012
Franson Joshua J – FXJ180000
Final Design Project
2. Introduction:
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit (CPU)
of a computer.
An ALU performs basic arithmetic and logic operations. Examples of arithmetic operations are
addition, subtraction, multiplication, and division. Examples of logic operations are
comparisons of values such as NOT, AND, and OR. In this project 16bit ALU where two 16bit
inputs are given and the output obtained will be a 32bit one.
3. Design constraints:
The main fix in the design of cells is that size is always inversely proportional to delay. In the
design of these cells we used Wp/Wn ratio close to 2.22. Though the value of 3 is most desired
to obtain minimum delay, the size parameter is also considered during the design. Hence the
size and delay parameters are compromised during this design.
Hence we fixed the width of pfet as 2.4um and nfet as 1.08um. Hence the Wp/Wn ratio is 2.22
The Complete Process:
• We designed layout and schematics for 9 cells such as Inverter, NAND2, NOR2, XOR2,
OAI21, OAI211, flipflop, Mux 2:1 and AOI22.
• Using cadence tool, the layout was designed without any errors and was matched with
the schematics respectively.
• All the cells were made to have the same height(10.66um) throughout the design to
eliminate spacing errors during later part of the process in automatic placement and
routing.
• The pins were kept at same axis with equal spacing of 0.48*n. The space between
boundary and pin was maintained at 0.72um(0.24+0.48*n)
• The operation of these cells was tested using the HSpice software and was ensured the
cells were working.
• The abstract view of the cells was generated which were used for generation of LEF and
ASCII files.
• Create library using the Siliconsmart software mentioning the operation of each cell and
their specifications.
• Now using the generated library file create mapped netlist for the actual Verilog code.
• Using modelsim software compare the waveforms of both the codes. They should
exactly match.
• Using the Encounter tool, automatic placement and routing process was done. The
encounter tool requires the LEF files and the mapped netlist Verilog code.
• Once the routing is done add the vias and export the DEF file to the cadence location.
• Now the layout and schematic for the overall Verilog file would be generated.
• Run DRC and LVS for the same as done for the cells designed above.
• Using the generated library file, mapped netlist Verilog file and the design constraints
generate the power timing analysis using Primetime software.
4. Verilog code:
module alu(
input [15:0] A,B, // ALU 16-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [31:0] Y, // ALU 32-bit Output
output CarryOut, // Carry Out Flag
input clk,
input reset
);
reg q;
reg [31:0] ALU_Result;
wire [16:0] tmp;
assign Y = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[16]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
6. ALU_Result = (A==B)?16'd1:16'd0 ;
default: ALU_Result = A + B ;
endcase
end
always @ ( posedge clk)
if (reset==1)
begin
q <= 1'b0;
end else if(reset==0) begin
q <= ALU_Result;
end
endmodule
Test bench:
`timescale 1ns / 1ps
module tb_alu;
//Inputs
reg[15:0] A,B;
reg[3:0] ALU_Sel;
//Outputs
wire[31:0] ALU_Result;
wire CarryOut;
// Verilog code for ALU
integer i;
7. alu test_unit(
A,B, // ALU 8-bit Inputs
ALU_Sel,// ALU Selection
ALU_Out, // ALU 8-bit Output
CarryOut // Carry Out Flag
);
initial begin
// hold reset state for 100 ns.
A = 16'h0A;
B = 8'h02;
ALU_Sel = 4'h0;
for (i=0;i<=31;i=i+1)
begin
ALU_Sel = ALU_Sel + 16'h01;
#10;
end
A = 16'hF6;
B = 16'h0A;
end
endmodule