Several key technology trends are redefining the boundaries of the traditional storage infrastructure stack: In a rapidly changing world of system interconnects, emerging memory media, and storage semantics, Server Designers and Storage Architects are engaging and collaborating like never before to exploit breakthrough technology capabilities. With the backdrop of Big Data volume, Cloud Data ubiquity and IoT Data velocity, Application Developers are entering the Post-POSIX world of real-time, high-frequency, low latency data management frameworks.   This session will address key technology trends in Storage, Networking, and Compute, as they define the parameters of a Memory Centric Architecture (MCA) and the Next Generation Data Center.

1. MT48
A flash into the future of storage
Flash meets emerging memories and the data center
changes forever!
Dan Cobb and Robert Hormuth
Dell EMC Fellows

2. 2
The Memory Hierarchy
70 years of feeding CPUs
“We are therefore forced to recognize the possibility of
constructing a hierarchy of memories, each of which
has greater capacity than the preceding but which is
less quickly accessible.”
U.S. Army Ordinance
Department Report
June 28, 1946
A. W. Burks, H. H. Goldstine & J. von Neumann
Preliminary Discussion of the Logical Design of an Electronic Computing Instrument

3. 3
Moore’s Law Amdahl’s Law
S = 1
f
s
+ f
p
/ N
I’m giving you more cores! I can’t use any more cores!
Moore’s Law meets Amdahl’s Law

4. 4
It’s not just a good idea, it’s the law.
Compute: The future ain’t what it used to be
• Frequency (power)
– Stalled by Ohm’s Law
• Density (cores)
– Moore’s law, stalled by Amdahl’s Law
• Software
– Wirth's (aka Gate’s) Law is NOT stalled
• Performance
– Challenged by all laws
• Cost
– Utilization & hot data
– What (else) can be put on a die?

5. 5

6. 6
What would you do with a million billion iops?
Media Progression
Today: HDD & NAND
– NAND ⋘ performance HDD
– NAND ⋙ capacity HDD
– IO density cooling for both
Tomorrow: Emerging memories
cheaper memory or faster storage?
– YES! Many use cases for 50ns ⋘ access times ⋘ 100µs
– Faster, better, more cost effective traditional storage
– New architectures for 3rd Platform & In-Memory workloads
– Caveat for Software Design: persistence ⋙ multi-threading

7. 7
“…it was the epoch of belief, it was the epoch of incredulity…”
Interconnect/Interface progression
Storage: strong open innovation agenda
• SATA, SAS: SW & HW compatibility accelerated adoption,
but legacy storage stack drag
• NVMe: Overnight Success, 7 years in the making
– reduced overhead for latency & parallelism
– good for NAND, mandatory for 1μs media
– design-center specific form-factors
• NVMe Over Fabrics: one ring to rule them all?
– proper layering, if the data-links play nice
– unprecedented interest from NIC, switch, SW, server, storage
Memory: details still emerging

8. 8
The SAN Storage Array: Case Study
NORTH-SOUTH: External network
• Interoperable, multi-path host connectivity
– Fibre Channel
– iSCSI/Ethernet
– NVMe-oF in the future
storageHW
platform
performance recoverability protectionpersistence
consistencysemanticspoolingplacement
device mgt provisioning security compliance
SAN
EW
reliability
server
server
server
availability servicability
server
appappappappappapp
internal fabric
EAST-WEST: Internal private fabric
• High-Availability services
– deterministic, resilient
– low latency, high bandwidth
– PCIe, Infiniband, Ethernet
• 100s ⋘ drives ⋘ 10,000
99.9999%
N
S

9. 9
External fabric
The ”server SAN”, aka SDS
EAST-WEST: General Purpose LAN – Ethernet/IP
• All traffic: data, data services, coherence
• 3 ⋘ servers ⋘ 1,000

10. 10
Unlock the media: take the CPU out of the data path.
The DMA Area Network: DSSD
Consider the humble NAND die:
• Media access time < 100μs; implies >10,000 IOPS
• 32KB reads implies >320 MB/s
• So a single SSD with 512 NAND die could deliver 5M IOPS & 160 GB/s
Rethinking the system from the media up:
• 18000 NAND die in parallel
• Resilience @ the system level
• Emerging Memory ready
• DMA & NVMe / RDMA & NVMe-oF
• Optimal SW data path

11. 11
In 1947, Burks, Goldstine and von Neumann …
outlined the design of another type of machine (a parallel machine this
time) which should be exceedingly fast, capable perhaps of 20,000
operations per second.
They pointed out that the outstanding problem in constructing such a
machine was in the development of a suitable memory,
all the contents of which were instantaneously accessible

12. 12
Required for memory area storage
Introducing the Memory Area Network
• Storage: has followed a logical progression:
– Local: SATA, SAS, NVMe (DMA)
– Remote: FC, iSCSI, iSER, NVMe-oF (RDMA)
– New physical form factors
• Memory: the path is not so clear
– What comes after DDR4/5?
– How to accommodate rich innovation in new media?
– What should SW developers do?
• Gen-Z
• CCIX?
• NVDIMM-*?
• CAPI?
• MCDRAM?
• HBM?
• HMC?
• NVLink?
• memkind?
• libpmem?

13. 13
For “born in the memory era” applications
The Memory-Centric Architecture
Memory Controller QPI
PCIe
DRAM
Operating System
Application
2nd Platform
Storage Centric
Future NVM
Storage
NAND/HDD
CPU
L1 L2 L3
Data Services
Storage
read/write
Tiered
Memory
Controller
Storage &
Memory Pool
NVM/NAND
/HDD
CPU
L1 L2 L3
3rd Platform
Memory Centric
Operating System
Application
Memory
load/store
• Persistence
• Resilience
• Protection
• Recoverability
• Pooling
• Virtualization
• Placement
• Sharing
• Workflow
• Protocol
• Semantics
• Consistency
• Aggregation
• Capacity

14. 14
Memory Centric Architecture Vision
• IT is ready for a revolution: Memory Centric Architecture
• Data velocity is increasing, Hot Data volume is growing - Applications are changing
• Information is monetized via processing speed: TIME = MONEY
• Real-Time 3rd Platform data management applications want all data near the CPU
• Architectural Evolution has slowed
• Today’s Storage/IO/Memory subsystems have become a bottleneck
• A shift to MCA will be a journey, with a collection of system technologies
– Interoperable standards will accelerate innovation, not hinder it
• Emerging Memories will play a significant role

15. 15
How do we get to a Memory Centric Architecture
• Problems to be solved
– What to do about DRAM?
– Future NVM at local node
– Future NVM technology at rack level
– Lowest Latency/Highest BW Cache Coherency IO for acceleration
– High BW/Low Latency Rack Scale Fabric
– OS & Application comprehension of different memory tiers and types
• Our industry needs to collaborate on new open standards to enable
innovation and accelerate adoption

16. 16
The Creation of a New Ecosystem
• A Memory Centric Architecture requires fundamental changes and new
technologies must be invented/improved
– Emerging Memory technologies will provide a critical ecosystem for MCA,
as diverse media types provide a variety of capabilities, capacities, cost
points & performance
– the memory subsystem must become an open innovation platform
• Aggressive innovation is required
• Open, interoperable standards will provide the tailwind