HDLs like VHDL and Verilog are used to describe digital logic circuits and systems. VHDL uses a programming-like syntax to describe entities with architectures, while Verilog can describe designs at different levels of abstraction from algorithms to transistor-level operations. Both support basic data types like integers and support common operators. They have conventions for naming and coding style to improve readability and debugging.

1. Hardware Description Languages (HDLs)
• HDLs are similar to programming languages but not exactly the same.
• We utilize a programming language to build or create software, whereas we use a
hardware description language to describe or express the behavioral characteristics of
digital logic circuits.
• We utilize HDLs for designing processors, motherboards, CPUs (i.e., computer chips), as
well as various other digital circuitry.
• Three main HDLs are
1) VHDL
2) Verilog
3) SystemVerilog

2. VHDL
• VHDL stands for Very High Speed Integrated Circuit (VHSIC) Hardware Description
Language (VHDL).It works on RTL (Register Transfer Level). RTL design involves
describing the behavior of a design as the transfers that occur between registers every
clock cycle. VHDL is strongly typed but case insensitive language. It serves best for high
level and complex designs.
• VHDL program contains..
1) Entity: Describes the interface of our design 3)Port: Ports/Pins used by entity.
2) Architecture: Describes underlying functionality of Entity
*Single entity can have more than one architecture.
EXAMPLE: entity and2 is
port( a: in std_logic; b: in std_logic; c: out std_logic);
end and2;
architecture and2_a of and2 is
begin
c <= a and b;
end and2_a;

3. VHDL
• Data Types: This is a classification objects/items/data that defines the possible set of
values which the objects/items/data belonging to that type may assume.
1) Bit: 2) Integer: integer number from
-2,147,483,647 to + 2,147,483,647
(i.e. size is 32 bits)
Example
VARIABLE a: INTEGER;
Variable Assignment operator :=
a := ‘1346’;
3) Std_logic: It is the most common data type used to hold a single bit value or to hold
multiple bits if std_logic_vector is used.
Example
SIGNAL s1: std_logic := ‘0’;
etc..

4. VHDL
• Naming Conventions: Designed to make your code easier to read, understand, and
debug. By following these rules, it also makes it easier for others to understand your
code.
• Enitities, Architectures, Functions Naming conventions:
Names should describe, in some way, what the block of code does
Names should be lowercase and use underscores to separate words
Entities should have unique names. Architecture need not have unique names as they
are linked to entities, but should have a name resembling their entity (eg. 'entity_arch’
or 'entity_rtl')
• Signal Naming Conventions
Use '<signal_name>_addr' for addresses and '<signal_name>_clk' for clocks
For active-low signals, using '<signal_name>_l' is preferred

5. VHDL
• Operators:
1) Arithmetic operators: +, -, *, /, not, etc. 4) Logical operators:
2) Shift operators:
3) Relational operators:
sll Shift left logical
srl Shift right logical
sla Shift left arithmetic
sra Shift right arithmetic
etc.
= Test for equality
/= Test for inequality
<= Test for less than or equal & assignment operator
(*to assign values to a variable)
>= Test for greater than or equal
< Test for less than
> Test for greater than
and Logical and
or Logical or
nand Logical complement of and
nor Logical complement of or
xor logical exclusive of or
xnor logical complement of exclusive of or

6. VHDL modelling styles
• 1. Data flow modeling (Design Equations)
Data flow modeling can be described based on the Boolean expression. It shows how the
data flows from input to output. It works on Concurrent execution.
• 2. Behavioral modeling (Explains Behaviour)
Behavioral modeling is used to execute statements sequentially. It shows that how the
system performs according to the current statement.
Behavioral modeling may contain Process statements, Sequential statements, Signal
assignment statements, and wait statements.
• 3. Structural modeling (Connection of sub modules)
Structural modeling is used to specify the functionality and structure of the circuit.
Structural modeling contain signal declarations, component instances, and port maps in
component instance.

7. VHDL behavioural modelling example

8. Bottom testing loop
• Loops implemented with the test at the bottom (a do loop) are called bottom-driven
loops.
• do while is a bottom tested loop.
do {….
………
………}
While(____)

9. Verilog
• Verilog stands for Verification and Logic.
• It works on RTL (Register Transfer Level). RTL design involves describing the behavior of
a design as the transfers that occur between registers every clock cycle.
• Verilog is loosely typed language (i.e., data types can be used in a mix and match way)
but case sensitive language. It serves better for low level and simple designs.
• Verilog can be used to describe designs at four levels of abstraction:
(i) Algorithmic level (much like c code with if, case and loop statements).
(ii) Register transfer level (RTL uses registers connected by Boolean equations).
(iii) Gate level (interconnected AND, NOR etc.).
(iv) Switch level (the switches are MOS transistors inside gates).

10. Verilog
• Data Types: This is a classification objects/items/data that defines the possible set of values
which the objects/items/data belonging to that type may assume.
1) Value set for data types 2) Integer: integer number from
-2,147,483,647 to + 2,147,483,647
(i.e. size is 32 bits)
Example
integer a;
assign a=63;
3) wire: It represents a physical wire in a circuit, so it can be read but can’t be assigned.
Example
wire c;
4) reg: Register data type is used to create a variable, representing register/registers.
Example
reg a; // single 1-bit register variable
reg [7:0] b, c; // two 8-bit register variables
5) Input, Output:
input a; // a is an input variable
output b, c; // b and c are output variables

11. Verilog
• Naming Conventions: Designed to make your code easier to read, understand, and
debug. By following these rules, it also makes it easier for others to understand your
code.
• Input naming convention:
input i_Clock;
• Output naming convention:
output o_Data;
• Register naming convention:
Reg r_Data;

12. Verilog
• Operators:
1) Arithmetic operators: +, -, *, /, etc. 4) Logical operators:
2) Shift operators:
3) Relational operators:
<< Shift left
>> Shift right
== Test for equality
!= Test for inequality
<= Test for less than or equal
>= Test for greater than or equal
< Test for less than
> Test for greater than
&& Logical and
|| Logical or
! Logical not