The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSPVLSICS Design
Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design SystemIOSRJVSP
There is need to develop various new design techniques in order to fulfil the demand of increased speed, reduced area for compactness and reduced power consumption. It is considered that improved other performance specifications such as less delay, high noise immunity and suitable ambient temperature conditions are the prime factors. In this paper two different techniques are used for designing a 4-bit Magnitude Comparator(MC) and then a comparison is made about area and average delay. First one is Transmission Gate (TG) technique and second one is GDI Technique. This paper describes the design of an Integrated Circuit (IC) layout for a 4-bit MC. The layout was designed by use of an open source software namely Electric VLSI Design System which is Electronic Design Automation (EDA) tool. LTspiceXVII is used as simulator to carry out the simulation work.
Area and Power Efficient Up-Down counter Design by Using Full Adder ModuleIJEEE
In this paper an area and power efficient 98T Up- Down counter design has been presented by using Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full adder modules has been used to design this Up-Down counter which consumes less area and power at 120 nm as compared to CMOS, TG and GDI full adder designs. The proposed Up-Down counter design is based on this area and power efficient 10 transistors PTL full adder module. The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 using 120nm technology. Results show that Area of proposed PTL Up- Down counter design is 1288.4 µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counter design consumes 111µW power at BSIM-4.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
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C0421013019
1. International Journal of Computational Engineering Research||Vol, 04||Issue, 2||
A More Effective Realization Of BCD Adder By Using A New
Reversible Logic BBCDC
Shefali Mamataj1,Biswajit Das2,Anurima Rahaman3
1
2
Assistant Professor, Department of ECE Murshidabad College of Engineering &Technology,Berhampore,
Assistant Professor, Department of CSE, Murshidabad College of Engineering &Technology,Berhampore
3
B.Tech Student, Department of AEIE, Future Institute of Engineering and Management,Sonarpur
Abstract:
Reversible logic is one of the emerging technologies having promising applications in quantum
computing nanotechnology, and low power CMOS design. The main purposes of designing reversible
logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. With the
advent of quantum computer and reversible logic, design and implementation of all devices has received
more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. This
paper represents a new reversible logic BBCDC and also a more effective realization of BCD adder by
using the proposed reversible logic. A comparative result is presented which shows that the proposed
design is more effective in terms of number of gates and number of garbage outputs than the existing
designs.
KEYWORDS: Reversible logic, Basic Reversible Gates, BCD adder , Reversible full adder, Constant
input, Garbage ,Quantum cost.
1. Introduction
I.
INTRODUCTION
In electronics hardware designing energy dissipation is one of the most important factor. Researchers
like Landauer have shown that for irreversible logic computations, each bit of information lost, generates kTln2
joules of heat energy, where k is Boltzmann‟s constant and T the absolute temperature at which computation is
performed [1]. Bennett showed that kTln2 energy dissipation would not occur, if a computation is carried out in
a reversible way, since the amount of energy dissipated in a system bears a direct relationship to the number of
bits erased during computation [2]. Reversible circuits are those circuits that do not lose information and
reversible computation in a system can be performed only when the system comprises of reversible gates. These
circuits can generate unique output vector from each input vector, and vice versa, that is, there is a one-to-one
mapping between input and output vectors According to Moore‟s law the numbers of transistors will double
every 18 months. Thus energy conservative devices are the need of the day. The amount of energy dissipated in
a system bears a direct relationship to the number of bits erased during computation. Reversible circuits are
those circuits that do not lose information A circuit will be reversible if input vector can be specifically retrieved
from output vectors and here is one to one correspondence between input and output [3]. A reversible logic
circuit should have the following features [5]:
• Use minimum number of reversible gates.
• Use minimum number of garbage outputs.
• Use minimum constant inputs.
Decimal arithmetic has found promising uses in the financial and commercial applications. This is due
to the precise calculations required in these applications as oppose to binary arithmetic where some of decimal
fractions can‟t be represented precisely [16].In the hardware design, binary computing is preferred over decimal
computing because of ease in building hardware based on binary number system. In spite of ease in building
binary hardware, most of the fractional decimal numbers such as 0.110 cannot be exactly represented in binary,
thus their approximate values are used for performing computations in binary hardware. Because the financial,
commercial, and Internet-based applications cannot tolerate errors generated by conversion between decimal
and binary formats, the decimal arithmetic is receiving significant attention and efforts are being accelerated to
build dedicated hardware based on decimal arithmetic [4].
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2. A More Effective Realization Of BCD Adder…
II.
BASIC REVERSIBLE LOGIC GATE
2.1.Reversible logic Function:
It is an n-input n-output logic function in which there is a one-to-one correspondence between the
inputs and the outputs. The reversible logic circuits must be constructed under two main constraints. They are
Fan-out is not permitted.
Loops or feedbacks are not permitted.
In the proposed design these two constraints along with the other parameters are optimized effectively .
The important parameters which play a major role in the design of an optimized reversible logic circuit are [1719] ,
Constants: This refers to the number of inputs that are to be maintained constant at either 0 or 1 in order to
synthesize the given logical function.
Garbage: This refers to the number of outputs which are not used in the synthesis of a given function. These are
very essential without which reversibility cannot be achieved.
Gate count: The number of reversible gates used to realize the function.
Flexibility: This refers to the universality of a reversible logic gate in realizing more functions.
Quantum cost: This refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated
knowing the number of primitive reversible logic gates (1X1 or 2X2 ) required to realize the circuit.
Gate levels: This refers to the number of levels in the circuit which are required to realize the given logic
functions.
2.2. Basic Reversible logic Gates
The important basic reversible logic gates are, Feynman gate [6] which is the only 2X2 reversible gate
which is as shown in the figure.(1a )and it is used most popularly by the designers for fan-out purposes. There is
also a double Feynman gate [7], Fredkin gate [8] and Toffoli gate [9],New Gate[10] , Peres gate[11] , all of
which can be used to realize important combinational functions and all are 3X3 reversible gates and are as
shown in the figure.(1b) to figure.(1e) .The figures also shows the switching functions for terminals.
Figure(1a) Feynman gate – 2X2 gate
Figure(1b) Fredkin gate – 3X3 gate
Figure.(1c) Toffoli gate – 3X 3 gate
Figure.(1d) New gate – 3X 3 gate
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3. A More Effective Realization Of BCD Adder…
Figure(1e) Peres gate – 3X 3 gate
There are other 4X4 gates some of which are specially designed for the realization of important combinational
circuit functions in addition to some basic functions. Some of the important 4X4 gates are, TSG gate [13],MKG
gate [12],HNG gate [14]etc, shown in figure(2a,2b,2c) all of which are very useful for the construction of
important reversible adders.
Figure( 2a) Block diagram of MKG Gate
Figure( 2b) Block diagram of HNG Gate
diagram
Figure (2c): TSG Gate Block
2.3.Reversible logic DKFG gate
A 4X4 reversible gate DKFG already had been proposed [20] shown in figure 2. In this gate the input
vector is given by 𝐼 𝑉=(0,A,𝐵,C) and the corresponding output vector is 𝑂 𝑉=(𝑃,𝑄,𝑅,𝑆).
. Figure(3a): DKFG reversible gate
We can use DKFG gate as a full-adder as shown in fig3b
.
Figure (3b): DKFG gate implemented as Full adder
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4. A More Effective Realization Of BCD Adder…
III.
PROPOSED 5 X 5 REVERSIBLE GATE
A 5X5 reversible gate BBCDC (Binary to BCD conversion ) logic has been proposed in this paper (See
Figure 4) for BCD adder circuit application. The Truth table for the corresponding gate is shown in TABLE I .
A closer look at the Truth Table reveals that the input pattern corresponding to a specific output pattern can be
uniquely determined and thereby maintaining that there is a one-to-one correspondence between the input vector
and the output vector. In this gate the input vector is given by 𝐼𝑉=(A,𝐵,C,D,E) and the corresponding output
vector is𝑂𝑉=(𝑃,𝑄,𝑅,𝑆,T)
Figure 4: BBCDC reversible gate
TABLE I TRUTH TABLE OF BBCDC
INPUTS
OUTPUTS
E
C
B
A
T
S
R
Q
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
1
0
0
0
1
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D
0
0
1
1
1
1
0
0
1
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5. A More Effective Realization Of BCD Adder…
IV.
CONVENTIONAL BCD ADDER CIRCUIT
A Binary Coded Decimal (BCD) adder is a circuit which adds two 4-bit BCD numbers in parallel and
produces a 4-bit BCD result. Fig. 5 shows the block diagram of conventional BCD adder. The circuit must
include the correction logic to produce valid BCD output. Two 4-bit BCD numbers A(A3A2A1A0) and
B(B3 B2B1B0) along with carry input is added using conventional 4-bit parallel adder, 4-bit sum and a carry is
taken out. If the carry output is set or if the result is greater than nine, binary 0110 is added to the intermediate
sum output with the help of second stage 4-bit parallel adder circuit shown in figure5. In a BCD adder, the
correction logic which generates the Cout is given by, Cout = S3S2 +S3S1+C4
Figure 5: Conventional BCD adder circuit
V.
PROPOSED BCD ADDER CIRCUIT
A BCD adder can be realized by using two parts, first part represents a four bit parallel adder and the
second part gives us the appropriate addition result in the form of BCD number. The 4-bit parallel adder can be
constructed using HNG gates or DKG gates or TSG gates or MKG gates. But we have designed the adder circuit
by using DKFG reversible gate as a full adder. The proposed BCD adder circuit is shown in figure 6. Here two
BCD numbers A(A3A2A1A0) and B (B3B2 B1B0) are to be added and we got the result of the BCD addition as
S‟3 S‟2 S‟1 S‟0 and final carry output K from the adder circuit. The minimum value of the one bit BCD addition
is 0(0000) and the maximum value should be 19(10011).
The BCD sum cannot be greater than 19 because the range of a one bit BCD number is 0-9.Now if
carry =1,then the maximum BCD sum will be 9+9+1=19.So in our proposed circuit we will get the maximum
BCD sum (19) in binary form as S‟3=0 , S‟2=0, S‟1=1, S‟0=1 and K=1 .But this is not the correct BCD form .We
will get the result in binary form(10011).So for getting the corrected form of BCD sum we have to convert this
binary sum into BCD form by using appropriate logic. So for this we have used here a new BBCDC logic for
this conversion. If we follow the truth table of BBCDC ,we can see that we can get the appropriate BCD
form11001 instead of 10011 .So here S3S2S1S0 is the corrected form of BCD sum and the minimum value is
CoutS3S2S1S0=00000 and the maximum value will be CoutS3S2S1S 0= 11001 which is the appropriate form of
BCD sum.
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6. A More Effective Realization Of BCD Adder…
Figure 6: Proposed BCD adder circuit
TABLE III COMPARISON OF EXISTING BCD ADDERS AND PROPOSED BCD ADDER
Name of circuit
I.
Different parameters
No. of No.
of No.
of
Garbage Constant
reversible
output
input
gates
BCD adder[21]
22
17
23
22
22
17
14
11
7
6
7
8
11
10
8
9
5
BCD adder[22]
BCD adder[23]
BCD adder[24]
BCD adder[25]
BCD adder[26]
PROPOSED BCD
adder
11
10
11
8
.
VI.
CONCLUSION
We have realized BCD adder circuit by using DKFG and BBCDC reversible gates and made
comparisons in TABLE II. The analysis of various implementations discussed is tabulated in TABLE II. It gives
the comparisons of the different designs in terms of the important design parameters like number of reversible
gates, number of garbage outputs, and number of constant inputs parameter. From the table it is observed that
the present proposal uses least number of gates producing least number of garbage outputs. The efficient design
of the BCD adder depends on the design methodology used for designing the reversible ripple carry adder and
the reversible binary to BCD converter. Thus for future research, efficient design schemes for reversible ripple
carry adder and the reversible binary to BCD converter is an interesting area to investigate. Alternate
optimization methods are under investigation as a future work.
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7. A More Effective Realization Of BCD Adder…
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