1) The document discusses the asynchronous and synchronous modes of the USART serial communication protocol for PIC microcontrollers. 2) In asynchronous mode, the USART can operate in either 8-bit or 9-bit mode and supports full-duplex communication. The baud rate is set using the SPBRG register. 3) In synchronous master mode, the USART generates the serial clock and can only transmit or receive data at a time (half-duplex). The baud rate formula is different. In synchronous slave mode, the USART receives the external serial clock.

1. Dept. : Computer Technology Eng.
Class : 3rd Year Undergraduate
Branch : Electronic and Communication
Subject : Digital Microcontroller
Lecture No. ( 17 )
Northern Technical University
Technical Eng. College/ Mosul
Prepared By:
Z.G.
V4-2021
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PIC Microcontroller
Serial Communication
Part (02)

2. USART (Asynchronous Mode, Full-Duplex)
USART (Asynchronous Mode, Full-Duplex)
The first step in using the USART in the asynchronous
mode is to activate the USART by setting (=1) the “SPEN”
bit in the “RCSTA” register. The Port C pins, RC6 and RC7,
must be configured with the TRISC register as “output” and
“input” respectively. Setting the “SPEN” bit enables the
“TX” pin (RC6) as the transmitted data output and the
(RC7) pin as the received data input.
Next, the “SYNC” bit of the “TXSTA” register must be
cleared (=0) to select the “Asynchronous” mode.
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3. USART (Asynchronous Mode, Full-Duplex)
Eight-bit vs. nine-bit transmission and reception is done
with the “TX9” bit of the “TXSTA” register and the “RX9”
bit of the “RCSTA” register, respectively. Setting each (=1)
enables the nine-bit operation while clearing them (=0)
enables the eight-bit operation. If the nine-bit operation is
enabled, the ninth transmitted data bit, “TX9D”, must be
set-up in the “TXSTA” register, and the ninth received data
bit, “RX9D”, can be found in the “RCSTA” register.
The baud rate must be selected next. There are two speeds
for the baud rate model. The user enters a value “X” in the
“SPBRG” register according to the formulas:
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4. USART (Asynchronous Mode, Full-Duplex)
Low-Speed Baud Rate = Fosc / (64 * (X + 1))
High-Speed Baud Rate = Fosc / (16 * (X + 1)).
The “BRGH” bit in the “TXSTA” register selects between these
“low-speed” and “high speed” models. If BRGH = 1, the “high-
speed” is selected and BRGH = 0 selects the “low-speed”. The
selection of these speeds is somewhat arbitrary in that one or the
other may give a better approximation to the desired baud rate,
and this is really what counts.
For example, suppose we want a baud rate of 19200 and the Fosc
= 4 MHz. For The “low-speed”, this gives SPBRG = 2 and the
approximate baud rate = 20833, which has a percent error of
8.5%. For the “high-speed”, this gives SPBRG = 12 and the
approximate baud rate = 19230 which has a percent error of
0.16%. Therefore, the “highs peed” selection is the better choice.
Last, the receiver must be enabled by setting (=1) the “CREN” bit
in the “RCSTA” register.
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5. USART (Asynchronous Mode, Full-Duplex)
The overall data format for the USART in the asynchronous
mode is transmission and reception with the least-
significant-bit first, in a non-return-to-zero (NRZ) format,
with the bit sequence as “start-bit, data-bits, stop-bit”, and
with no internally-generated parity bits.
The transmitter is enabled by setting (=1) the “TXEN” bit in
the “TXSTA”. To send data for output, write the data to the
“TXREG” register. (If the nine-bit mode is set, the “TX9D”
data bit must be set-up first and then write the other part, the
byte, to the “TXREG” register.
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6. USART (Asynchronous Mode, Full-Duplex)
There is a “transmitter” interrupt flag, “TXIF”, which is set
when the “TXREG” register is empty and waiting for the
next byte to send. That is, when a data byte is placed in the
“TXREG” register, the byte is shifted out, and, when the
“TXREG” is empty, the interrupt flag is set. The “TXIF”
flag cannot be reset in software. It is only reset by writing
another byte to the “TXREG” register. If there is no more
data to transmit, the interrupt process can only be disabled
by disabling the “TXIE” interruptenable bit.
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7. USART (Asynchronous Mode, Full-Duplex)
To receive a data byte, the “receive” interrupt flag, “RCIF”,
is set when a new byte is received, and will generate an
interrupt if it is enabled. The “RCIF” bit is automatically
reset when the software reads the data from the “RCREG”
data register. (If the nine-bit mode is set, the “RX9D” data
bit in the “RCSTA” register must be read before reading the
“RCREG” data.)
Another feature that is available in the nine-bit
asynchronous mode is “automatic address detection”. This is
used for “multi-PIC” or “multi-device” operations where
each device has a nine-bit “address” and it will respond to
the transmitting PIC only when the address matches the
address sent to it.
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8. USART (Asynchronous Mode, Full-Duplex)
To select this mode of operation, set-up the PIC in nine-bit
asynchronous mode and set (=1) the “ADDEN” bit in the
“RCSTA” register. Also enable the receiver interrupt with
the “RCIE” bit (RCIE = 1). When the interrupt occurs, read
the nine data bits, interpret them as an address, and see if the
address matches the user-defined address.
If it does, clear (=0) the “ADDEN” bit to allow the software
to read the data to follow.
The address is distinguished from the data by setting the
ninth-bit of the address to one (=1). The ninth-bit of the data
will be zero (=0).
It should be noted that the asynchronous USART mode is
halted if the CPU enters, the “Sleep” state.
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9. USART (Asynchronous Mode, Full-Duplex)
There are two receiver-error condition bits that need to be
discussed. These are the “OERR” bit meaning “Overrun
Error” and “FERR” meaning “Framing Error”. Both of these
bits are in the “RCSTA” register.
The “RCREG” register where the data comes in is double-
buffered so that it can store two bytes in succession. If a
third data byte comes in, without the first two having been
read, the “OERR” bit will be set (=1) to indicate “Overrun
Error”. When this happens, the third data byte is lost and the
whole receive process is inhibited. To correct and reset this
error, the “RCREG” register must be emptied and the
“OERR” can be reset only indirectly by doing:
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10. USART (Asynchronous Mode, Full-Duplex)
BCF RCSTA,CREN
BSF RCSTA,CREN.
The “Framing Error” condition, indicated by the “FERR” bit
is set (=1) if a received data byte has an illegal “Stop” bit
indicating that the data is illegal. This error condition does
not inhibit the receive process and does not need to be
cleared. A new “FERR” value will appear when the
“RCREG” data register is read. Therefore, check the
“FERR” bit before reading the “RCREG” to get the current
“FERR” value.
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11. USART (Synchronous, Master Mode)
USART (Synchronous, Master Mode)
Both the synchronous master mode and the synchronous
slave mode run the USART as “half-duplex” meaning that
the data cannot be transmitted and received at the same time.
The primary difference between the master mode and the
slave mode is that the master mode generates the serial
clock while the slave mode receives the external serial
clock.
Many features, bits, and conditions of the synchronous
master mode are similar to the asynchronous mode. This
section will illustrate only the differences between these
modes.
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12. USART (Synchronous, Master Mode)
The baud rate generator works with a model and formula different from the
asynchronous mode and the “BRGH” bit, which was the speed control, has
no meaning.
The baud rate is:
Baud Rate = Fosc / (4 * (X + 1))
Where “X” is the value written into the “SPBRG” register. This allows
for much higher baud rates.
The “Sleep” mode halts the synchronous master mode.
The “Address Detection” mode is not available in the synchronous master
mode.
The Port C pins, RC6 and RC7,are set up as before. The clock (CK) is sent
on RC6 while the data is both sent and received one way at a time, on RC7
(DT).
The “CSRC” bit and the “SYNC” bit, both of the “TXSTA” register, must
be set (=1) for the synchronous master mode.
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13. USART (Synchronous, Master Mode)
The operation of the USART in the synchronous master mode is more
complicated due to the restriction of doing only half-duplex
communications.
The “TXEN” bit of the “TXSTA” register and the “CREN” bit of the
“RCSTA” register must not both be set (=1) at the same time – only one or
the other is to be set (=1) at any one time.
To transmit data, the “TXEN” bit must be set (=1) and the “CREN” bit must
be cleared (=0). To receive data, the “TXEN” bit must be cleared (=0) and
the “CREN” bit must be set (=1).
All other things are equal. In the receive mode, the data is sampled on the
falling edge of the clock and, in transmit mode, the data is shifted on the
rising edge of the clock and is stable on the falling edge.
One exception is the possibility of receiving one single byte during the
transmission of (typically) a stream of transmitted data bytes. This is done
by setting the “SREN” bit (=1) of the “RCSTA” register while the “TXEN”
bit of the “TXSTA” register is set (=1). When a single byte is received, the
“SREN” bit is cleared (=0) automatically.
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14. USART (Synchronous, Slave Mode)
The differences between the synchronous slave mode and the other two
USART modes. Since the synchronous slave mode does not generate a
serial data clock, but receives it externally, there is no need to set-up the
“SPBRG” register to generate baud rates. The Port C pins, RC6 and RC7,
must both be set-up as “inputs” using the TRISC” register. The “CSRC” bit
of the “TXSTA” register must now be cleared (=0) for the synchronous
slave mode. The “single byte receive” option using the “SREN” bit is
disabled in the slave mode. The “either-or” nature of the “TXEN” and
“CREN” bits is still the same as in the synchronous master mode.
The reception or transmission of data in the slave mode can awaken the
CPU from “Sleep”.
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