This document provides information about the 8086 microprocessor system architecture including: 1. Block diagrams showing the connections between the 8086 MPU, memory, I/O devices and support chips. 2. Descriptions of the address/data bus, control signals, and memory/I/O interfacing. 3. Explanations of logic voltage levels, fan-out specifications and tri-state buffers for interfacing TTL devices to the 8086.

2. Mode
Select MN/MX’
Interrupt
interface
8086 MPU
Power supply
Vcc GND
INTR
_____
INTA
_____
TEST
NMI
RESET
HOLD
HLDA
Address / data bus
AD0-AD15,
A16/S3-A19/S6
ALE
____
BHE/S7
M/IO’
DT/R’
___
RD
___
WR
____
DEN
READY
CLK
DMA
interface
Memory/IO
controls

3. To avoid
conflict

4. MEMORY
ADDRESS DATA
WR
OE
CE
MWR
MRD
CS

6. D  O/P
Transparency
Last O/P
Maintained
(latched)
High Impedance
Tri-State
AD0
A0
AD1
A1
ALE
?

7. A0-
A15
D0-
D15
A0-
A15
74LS373
TRI-STATE
LATCH
8086
µP
MEM
or
IO
DEVICE
ALE
AD0-AD15 A0-A15

8. A0-A15, A16-A19
?
LATCH
O/P

12. Standard TTL Output and Inputs Voltage Levels
Guaranteed
Output Levels Accepted
Input Levels
0-Level
Noise Margin
1-Level
Noise Margin
5.0 V
Vcc
Forbidden
Region
0 Logic Level
1 Logic Level

13. OFF
ON
Standard
TTL Gate
I/P
O/P can sink up to
16 mA max
An I/P sources
up to 1.6 mA
0-level Fanout = Maximum number of inputs that the output can support
= 16 mA/1.6 mA = 10
Fan out for a standard TTL output
How many inputs can an output support?
(2) For the 1 logic Level: (output “sources” current)
O/P can source up to
400 mA max
I/P sinks
up to 40 mA 1-Level fan out = 10 also
OFF
ON
(1) For the 0 logic Level: (output “sinks” current)
0
1
If different,
take the smallest
of the two numbers
?
?

14. LOGIC LEVEL VOLTAGE CURRENT
0 0.8V Max +10µA Max
1 2.0V Min -10µA Min
LOGIC LEVEL VOLTAGE CURRENT
0 0.45V Max 2.0mA Max
1 2.4V Min -400µ A Max
Input pins
Output pins
mP
*
* = 16 mA for standard 74 TTL
# = 0.40 V for standard 74 TTL
# *
#
0 level fan-out to TTL gate = 2  1.6  1 (8086/88 mP)
= 16  1.6 = 10
(for standard 74 TTL O/P)
A processor output can drive:
• One 74XX input, or
• One 74SXX input, or
• Five 74LSXX inputs, or
• Ten 74ALSXX inputs, or
• Ten 74HCXX inputs
8086/88 mp does not strictly comply
with the DC characteristics
of the TTL family
+: Current into pin (sink)
- : Current out of pin (source)
Two problems:
- Lower fanout
- Lower noise margin
Guaranteed
Output levels
Accepted
Input levels
0 level noise margin = 0.8 – 0.45 = 0.35 V (mP)
= 0.8 – 0.40 = 0.40 V
(for standard 74 TTL O/P)
* = 1.6 mA for standard 74 TTL
# = 40 mA for standard 74 TTL

16. Used for unidirectional
Signals only

18. MEMORY
ADDRESS DATA
WR
OE
CE
MWR
MRD
CS

19. Used for Bidirectional
Signals

20. 0
0

21. 1
0

25. DATA BUS
WITHOUT TRISTATE
CONTROL
DATA BUS
DATA BUS
MEMORY MEMORY

26. DATA BUS
WITH A TRISTATE
CONTROL
DATA BUS
DATA BUS
MEMORY MEMORY

27. Data
bus
RAM 2M ´ 8
Address
bus
21 bits
Control
bus
20 bits
EN
EN
RAM 2
1M ´ 8
RAM 1
1M ´ 8
8 bits
8 bits
8 bits
20 bits

28. A1-A13
D0-D7
74LS138
A14
A15
A16
M/ IO
A0
G2A
G2B
G1
A
B
C
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
2764
8KX8
8KX8
CS
CS
CS
CS
CS
CS
CS
CS
A17
A18
A19
RD
WR
00000-03FFE
04000-07FFE
08000-0BFFE
0C000-0FFFE
10000-13FFE
14000-17FFE
18000-1BFFE
1C000-1FFFE
LOW BANK

29. 8086
MPU
DATA
RD
DEN
DT/R
ALE
BHE/S7
M/IO
AD0-AD15,
A16/S3-
A19/S6
WR
DIR
EN
G EN
EN
ADDRESS
DECODER
8KX8
8KX8
MEMORY
CS
CS
ADDRESS
OE
WR
74LS245
74LS244
74LS373
74LS138

30. 1. Draw the complete block diagram for an 8086
Microprocessor system with 2Kx16 EPROM and
2x2Kx16 RAM.
2. Redraw the same block diagram in detail assigning
the EPROM start address at (FF000) and the
RAM start address at (00000) .
3. Sketch the logical memory representation for the
system in paragraph 2 above.