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BUS DRIVER.pptx
- 2. Mode Select MN/MX’ Interrupt interface 8086 MPU Powersupply Vcc GND INTR _____ INTA _____ TEST NMI RESET HOLD HLDA Address / data bus AD0-AD15, A16/S3-A19/S6 ALE ____ BHE/S7 M/IO’ DT/R’ ___ RD ___ WR ____ DEN READY CLK DMA interface Memory/IO controls
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- 6. D O/P Transparency LastO/P Maintained (latched) High Impedance Tri-State AD0 A0 AD1 A1 ALE ?
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- 12. Standard TTL Outputand Inputs Voltage Levels Guaranteed Output Levels Accepted Input Levels 0-Level Noise Margin 1-Level Noise Margin 5.0 V Vcc Forbidden Region 0 Logic Level 1 Logic Level
- 13. OFF ON Standard TTL Gate I/P O/P cansink up to 16 mA max An I/P sources up to 1.6 mA 0-level Fanout = Maximum number of inputs that the output can support = 16 mA/1.6 mA = 10 Fan out for a standard TTL output How many inputs can an output support? (2) For the 1 logic Level: (output “sources” current) O/P can source up to 400 mA max I/P sinks up to 40 mA 1-Level fan out = 10 also OFF ON (1) For the 0 logic Level: (output “sinks” current) 0 1 If different, take the smallest of the two numbers ? ?
- 14. LOGIC LEVEL VOLTAGECURRENT 0 0.8V Max +10µA Max 1 2.0V Min -10µA Min LOGIC LEVEL VOLTAGE CURRENT 0 0.45V Max 2.0mA Max 1 2.4V Min -400µ A Max Input pins Output pins mP * * = 16 mA for standard 74 TTL # = 0.40 V for standard 74 TTL # * # 0 level fan-out to TTL gate = 2 1.6 1 (8086/88 mP) = 16 1.6 = 10 (for standard 74 TTL O/P) A processor output can drive: • One 74XX input, or • One 74SXX input, or • Five 74LSXX inputs, or • Ten 74ALSXX inputs, or • Ten 74HCXX inputs 8086/88 mp does not strictly comply with the DC characteristics of the TTL family +: Current into pin (sink) - : Current out of pin (source) Two problems: - Lower fanout - Lower noise margin Guaranteed Output levels Accepted Input levels 0 level noise margin = 0.8 – 0.45 = 0.35 V (mP) = 0.8 – 0.40 = 0.40 V (for standard 74 TTL O/P) * = 1.6 mA for standard 74 TTL # = 40 mA for standard 74 TTL
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- 25. DATA BUS WITHOUT TRISTATE CONTROL DATABUS DATA BUS MEMORY MEMORY
- 26. DATA BUS WITH ATRISTATE CONTROL DATA BUS DATA BUS MEMORY MEMORY
- 27. Data bus RAM 2M ´8 Address bus 21 bits Control bus 20 bits EN EN RAM 2 1M ´ 8 RAM 1 1M ´ 8 8 bits 8 bits 8 bits 20 bits
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- 30. 1. Draw thecomplete block diagram for an 8086 Microprocessor system with 2Kx16 EPROM and 2x2Kx16 RAM. 2. Redraw the same block diagram in detail assigning the EPROM start address at (FF000) and the RAM start address at (00000) . 3. Sketch the logical memory representation for the system in paragraph 2 above.