SerialCommInterface

1. Popular Serial
Communication Interfaces
09/13/2025

2. Outline
• Synchronous Serial Interfaces
• SPI (Serial Peripheral Interface)
• I2
C (Inter-Integrated Circuit Bus)
• Asynchronous Serial Interfaces
• RS-232C
• RS-422
• RS-485

3. Synchronous Serial Interfaces

4. Serial Peripheral Interface
• SPI was developed by Motorola in 1980
• Synchronous serial protocol
• The master (CPU) and the slave (peripheral) are synchronized with a clock generated by
the master.
• Four wire interface
• MOSI: Master Out Slave In
• MISO: Master In Slave Out
• SCLK/SCK: Serial Clock
• /CS: Chip Select or /SS: Slave Select

5. Serial Peripheral Interface (cont’d.)
• SPI transmission
• Both masters and slaves contain a serial shift register
• Upon the completion of data transmission, the contents of the two shift
registers are exchanged
• Both a write and a read operation are performed with the slave
simultaneously

6. Serial Peripheral Interface (cont’d.)
• SPI transmission
MSB 7
6
5
4
3
2
1
LSB 0
MSB 7
6
5
4
3
2
1
LSB 0
Master Slave

7. Serial Peripheral Interface (cont’d.)
• Daisy-chaining three SPI devices
• Not all SPI device supports daisy-chains

8. Four Modes of SPI Operations
• Clock polarity
• Low clock polarity
• High clock polarity
Idle
Transfer
SCK
Idle
Transfer
SCK

9. Four Modes of SPI Operations (cont’d.)
• Clock polarity & clock phase
Idle
Transfer
SCK
Idle
Transfer
SCK
Low clock polarity
High clock polarity
Clock phase 0 Clock phase 1

10. Four Modes of SPI Operations (cont’d.)

11. Four Modes of SPI Operations (cont’d.)

12. Four Modes of SPI Operations (cont’d.)

13. Four Modes of SPI Operations (cont’d.)

14. Overview of I2
C
• Inter-Integrated Circuit (I2
C) bus
• developed in 1982
• by Philips labs in Eindhoven, Netherlands
• similar to SPI
• synchronous serial communication protocol
• two-wire interface
• SDA: serial data (open drain)
• SCL: serial clock (open drain)
• low speed (100 kbps in standard mode, and 400 kbps in fast mode)
• bidirectional
• Synchronous to a common clock

15. Open Drain/Collector Logic Gates
• Logic gates without an output pull-up device
• Need to use a pull-up resistor

16. Overview of I2
C
• I2
C bus
• A multi-master bus
• Each device has a unique address and can operate as either
• a transmitter (a bus master),
• a receiver (a bus slave), or
• both

17. Idle
• Both SDA and SCL are high
Idle

18. Start Condition
• A I2C transaction begins with a start condition
Start

19. Transmitting a Bit
• The bit must become valid on SDA while SCL is low.
• The bit is sampled on the rising edge of SCL and must remain valid
until SCL goes low once more.
Sample Sample
Transmitter:
Prepare Data
Receiver:
Read Data
Receiver:
Read Data

20. Acknowledge
• Each byte transmitted must be acknowledged by the receiver.
• Upon the transmission of the eighth data bit, the master releases the
data line SDA and generates an additional clock pulse on SCL. Then,
the receiver has to pull SDA low. Fail to do so would cause a
transmission error.

21. Transmitting a Byte
• MSB is transmitted first
• Acknowledge bit

22. Stop condition
• The transaction completes by SCL returning high followed by SDA.
This is known as a “STOP condition.”
Stop

23. Addressing
• The first byte of an I2C transfer contains
• 7-bit address, and
• 1-bit data direction (Read/Write)

24. I2
C Packet
1
0
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0
Read: 1
Write: 0

25. Asynchronous Serial Interfaces

26. UARTs
• Universal Asynchronous Receiver Transmitter
• RS-232 was first introduced in 1960
• Asynchronous: no clock is transmitted with the serial data.
• Matched local clocks

27. UARTs (cont’d.)
• Universal Asynchronous Receiver Transmitter
• Baud rate (bit/sec)

28. UARTs (cont’d.)
• UART bit stream
• 1 start bit
• 7/8 data bits
• 1/0 parity bit
• 1/1.5/2 stop bit(s):

29. 8052 Timer2 Baud Rate Generator
• T2CON

30. 8052 Timer2 Baud Rate Generator
• T2CON

31. 8052 Timer2 Baud Rate Generator
• Baud Rate

32. 8052 Timer2 Baud Rate Generator
• Baud Rate Calculator
• https://www.keil.com/c51/baudrate.asp

33. Error Detection
• Parity (Hardware)
• Even parity: even number of 1’s
• E.g., 11101011
• Odd parity: odd number of 1’s
• E.g., 00101101
• Able to detect 1-bit error
• More than 2 bits?
• Consider using the Cyclic Redundancy Check (CRC) algorithm

34. RS-232C
• Unbalanced: the voltage level of a data bit being transmitted is
referenced to local ground.
• High: -5 to -15 V
• Low: 5 to 15 V
• Max. cable length: 15 m

35. RS-232C (cont’d.)
• Data Terminal Equipment (DTE)
• Data Communication Equipment (DCE): Modem

36. RS-232C (cont’d.)

37. RS-232C (cont’d.)

38. RS-232C (cont’d.)
• Handshaking: Hardware, Software, or None
• Transmitter waits for a ready signal from receiver
• None handshaking
• Hardware handshaking: CTS, RTS
• Software handshaking: XON/XOFF
• XON: 0x11
• XOFF: 0x13
Transmitter Receiver
RTS
CTS

39. RS-232C (cont’d.)
• Implementing an RS-232C Interface

40. RS-232C (cont’d.)
• Using a Serial Port as a Power Supply

41. RS-422
• Twisted pairs
• Max. cable length: 1,200 m

42. RS-485
• Variation of RS-422
• Max. cable length: 1,200 m

43. 8051/8052 UART
• Special Function Registers

44. 8051/8052 UART
• SCON: Serial Port Control Register

45. 8051/8052 UART
• SCON: Serial Port Control Register
• TI: Transmit Interrupt Flag
• RI: Receive Interrupt Flag

46. 8051/8052 UART
• UART Interrupt

47. Interrupt Service Routine
• Interrupt number and register bank
In main program, SBUF = obuf[0]; oidx = 1;
void timer0_isr(void) __interrupt (4) __using(3)
{
if (TI) {
…
SBUF = obuf[o_idx++];
} else if (RI) {
ibuf[i_idx++] = SBUF;
…
}
}