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Adaptive Output Stage for High Efficiency Class D Audio
Amplifier With High PSR Techniques
Omar Ake Xacur (723009570)
ECEN 607: Advanced Analog Circuit Design Techniques, Spring 2016
May 6, 2016
1 Abstract
An adaptive output stage Class D Amplifier for high efficiency in a wide range of power
outputs is presented in this Project Report. This work make use of techniques to enhance
the PSR. This work achieve a efficiency above 90% in low output power, a PSR of 69dB at
217Hz and a THD of 56dB. The design was implemented using 0.13−µm CMOS technology.
2 Introduction
Audio power amplifiers are electronic devices that take low-power audio signals and amplify
it to a suitable level to drive a speaker. This is accomplish by multiples stages of signal
processing that are low-powered and a final stage output to deliver high-power.
In modern days, audio amplifiers are around every corner. TVs, cars, computers, cell-
phones, are just a few examples of where one can find this devices.
2.1 Class D Audio Amplifiers
A Class D Audio Amplifier (CDA) is a electronic amplifier in which the output stage
operates as electronic switches. The signal to be amplified is modulated to Pulse Width
Modulation (PWM) at high frequencies, this making the output switches change between
fully conducting to non-conducting mode. After the PWM signal is amplified, a passive low
1

Omar A. Xacur (723009570) ECEN 607: Final Project Report
pass filter eliminate the high frequencies of the modulated signal and convert the PWM to
the original input.
(a) Open Loop.
(b) Closed Loop.
Figure 1: Typical CDA Topologies.
2.2 Statement of the problem
2.2.1 Efficiency
Although an efficiency of over 90% can be achieve with a well design CDA, implementations
of CDAs only take into account when the output is operating a light load. For small output
power the efficiency of the CDA deteriorate. Figure 2 Shows the deteriorate efficiency at
low power output levels.
Figure 2: Efficiency vs Output Power
2

2.2.2 Power Supply Noise to Signal
For its high efficiency, Class D Amplifiers are a widely used in mobile devices such as
cellphones and laptops. Often, the CDA is directly connected to the battery to provide
the maximum power available to the load, which is most of the time connected to RF and
digital circuits that can ad noise to the power supply. For that mater, a high rejection of
the noise in the power supply is needed in the topology of the CDA to not compromise the
fidelity of the audio.
2.2.3 Shifter Level
Following the idea of having the output of the CDA directly connected to the battery,
this work is implemented with two different levels of power supply. Since the technology
(IBM 130nm CMOS) provide large voltage transistors, the output will be connected to a
3.3 voltage supply while the rest of the circuit will be fed with a 1.2 voltage supply.
3 Background
3.1 Efficiency
Power Efficiency (η) is one of the mos important metrics for CDAs. Efficiency determine
the amount of power dissipated in the load versus the amount of power dissipated by the
battery.
η =
Pout
Pin
(1)
Assuming ideal conditions, the efficiency of a CDA can be expressed as:
η =
RL
Ron + RL
(2)
Where Ron is the on resistance of the transistor.
Unfortunately, Equation ( 2) is never the case in reality. Due the desired low resistance,
the output transistor are large transistors at the output stage, provide also large parasitic
capacitances.
A more accurate value for efficiency can be calculated with:
3

η =
Pout
Pin
=
Pin − PL
Pin
=
Po
Po + PL
(3)
Where PL is the power loss in the circuit and is define as:
PL = Pcd + Psw + Psc + PQ (4)
Pcd = Conduction losses due Ron.
Psw = Switching losses due charge and discharge of parasitics.
Psc = Short Circuit losses.
PQ = Quiescent power losses.
Previous works in Class D audio amplifiers only report the efficiency for a given load,
usually 8 ohms or 4 ohms. Nevertheless, in DC-DC converters the efficiency for different
output currents, and since DC-DC converters use a similar output stage as in the CDA, the
work done in that area is used as reference for the work in this project.
Figure 3: Results of [1]
[1] use a PMOS and NMOS output stage partitioned in three independently controlled
segments. The segments were created using identical unit cells connected in parallel to
achiever a binary weighting.
4

3.2 PSR
Various works have been done regarding the enhancement of the PSR in the CDA. Some
works include high order compensator ﬁlters or bridge-tie loads, that usually bring trade-oﬀ
of power consumption or active area. A Feed-Forward technique is also implemented to
achieve high PSR in the CDA.
Figure 4: FFPSNC Technique Model [2]
The Feed-Forward module inject the noise into the system with the correct gain and
polarity to cancel the noise of the supply that can achieve a PSR of 83dB. [2]
5

4 Proposed Solution
Based in the idea of [1], the proposed solution is to have an adaptive output stage for
diﬀerent power output. A ﬁnite state machine will be choosing the optimal output stage
for a given output power.
Figure 5: Region of losses
Knowing the principal losses in any given region of power output, an optimal CDA
output stage can be designed.
Low Output Power Medium Output Power High Output Power
PL = Psw = V 2
DDCpfsw PL = Psw + Pcd = PL = Pcd = I2
outRon
V 2
DDCpfsw + I2
outRon
Table 1: Losses by region of power consumption
To not compromise the PSR in the design, the Feed-Forward technique mentioned in
previous section is implemented in this work to achieve high PSR performance.
6

5 Circuit Diagram, Explanation and Design Procedure
Figure 6: Diagram of Proposed Idea
5.1 Output Stages
Three different output drivers were design for the implementation of the proposal solution.
With the values of the power losses for each region given in Table 1, the optimal Width
for the transistor can be calculated.
5.1.1 Low Power
When the system is working with low power, the main source of power losses is the switching
losses, therefore, the efficiency can be expressed as:
η =
Pout
Pout + Psw
(5)
The expression for Cp is given by:
Cp ≈ WLCox (6)
The optimal value for W (Wopt) for a low power consumption can be found by:
Wopt =
1
8LCoxRLfsw
(1 − η)
η
(7)
For a given efficiency, load and switching frequency.
7

5.1.2 Medium Power
Using:
Ron =
L
Wµn,pCox(Vgs − VT )
(8)
the losses of the medium power consumption can be represent as follow;
PL =
I2
outL
Wµn,pCox(Vgs − VT )
+ V 2
DDfswWLCox (9)
by derive PL with respect W, the Wopt can be found:
Wopt =
Iout
VDDCox
1
fswµn,p(VDD − VT )
(10)
5.1.3 High Power
Finally, for the high power region, since the only loss assumed is from conduction,the
transistor can be designed to have the On Resistance desired for a given eﬃciency:
Ron =
1 − η
η
RL (11)
(a) Parasitic Capacitance vs Width. (b) On Resistance vs Width.
Figure 7: On Resistance and Gate Capacitance of the transistors.
For the three output stages the Length of the transistors is always set at the minimum
to reduce the parasitic capacitances.
8

Figure 8: FFPSNC Circuit
5.2 FFPSNC
The transfer function of the FFPSNC technique shown in Figure 4 is given by:
VO(s)
VN (s)
=
D 1 − GFF (s) GM (s)
D
1 + GC(s)GM (s)β(s)
(12)
If GFF (s) = D
GM (s) a complete cancellation of the Supply noise would be achieved. R5/R6
implement GFF . To cancellate GM /D, GFF = D/GM . R3 − R4 are chosen to provide
unity gain from VC to VM . R7 − R6 are chosen to set common mode in the negative input.
The ampliﬁer used for this module was a two stage miller compensated ampliﬁer with
GBW of 12MHz and gain of 56dB.
5.3 Non Overlapping Clock and Drivers
To avoid short circuit periods, a non overlapping clock needs to be implemented. The
schematic is shown in Figure 9. This circuit is implemented with logical gates NANDs and
NOTs. The sizes of the transistors were kept at a ratio of 3:1 between PMOS and NMOS.
For the driver, the schematic in Figure 10 was implemented, the sizes of every inverter
is given by An(Wp1,n1) where An is given by:
An
=
CLoad
Cin
1
N
(13)
The output signal of the non overlapping and drivers connected to the output stage is
shown in Figure 11:
9

Figure 9: Non Overlapping Schematic
Figure 10: Driver Schematic
Figure 11: Voltage at the Gate of the Output Stages
10

6 Results
In this section, the results of the implemented circuits are shown.
Figure 12: Behaviour of the individual stages
Figure 13: Proposed Solution vs One Stage CDA
11

(a) PSR without FFPSNC module
(b) PSR with FFPSNC module.
Figure 14: PSR Simulation at 217Hz.
Figure 15: Total Harmonic Distortion Simulation
12

7 Simulate the temperature and noise.
Figure 16: Eﬃciency Changes with the Temperature
Figure 17: Noise Simulation of the entire Class D ampliﬁer
13

8 Corners Simulations.
Figure 18: Efficiency across all the corners of the technology
Since the output stages are large, small changes in the corners affect little to nothing
at the final efficiency of the CDA. As we can see in the figure above, in the worst case the
efficiency still over 94%.
9 Calculation vs Simulation
Stage WPMOS/WNMOS(mm) Efficiency (%)
Calculated Simulated Calculated Simulated
Low-Power 1/0.9 1/0.9 96 94.5
Medium-Power 4/1.5 3/2 96 94
High-Power 16.7/12.9 16/12 96 95
Table 2: Calculated vs Simulated parameters
The changes between the calculated and the simulated were to have an even number of
fingers for future layout work.
14

10 Discussion of Results with other reported results and sug-
gested improvements
The results for the output stage were favourables having an efficiency above 90% and an
enhancement little over 10%, but still this work can be considerate as a work in progress since
the PSR and THD are not competitive with another design in the market. Furthermore,
the reported results are measured with the fabricated device. This work is pretended to be
a starting point in the development of a competitive CDA.
10.1 Future Work
To improve the results of this projects, the FFPSNC needs to be revised carefully to improve
the PSR. Currently, due lack of time, the finite machine was not implemented, a research
into previous implementations of finite states needs to be done. Also, a inquire into the
enhancement of the THD needs to be done.
Parameter This work [2] [1]
Filter Order 1 1 NA
PSR(dB) 69 83 NA
η(%) 95 94 89
THD (%) 0.143 0.0149 NA
Supply(V) 3.3 1.8 4.2
Fsw(KHz) 500 500 4000
η Improvement 10 NA 7.5
Table 3: Comparison Table
References
[1] Oliver Trescases, et. al. A Digitally Controlled DC-DC Converter Module with a Seg-
mented Output Stage For Optimized Efficiency, International Symposium on Power
Semiconductors Devices & IC’s, June, 2006 Naples, Italy
15

[2] A.I. Colli-Menchi; J. Torres; E. Snchez-Sinencio, A Feed-Forward Power-Supply Noise
Cancellation Technique for Single-Ended Class-D Audio Amplifiers, IEEE Journal of
Solid-State Circuits , vol.49, no.3, pp.718-728, March 2014
[3] Texas Instruments Inc., Dallas, TX, USA, TLV320AIC3107: Low-Power Stereo Au-
dio Codec With Integrated Mono Class-D Amplifier, Apr. 2009 [Online]. Available:
http://www.ti.com/lit/ds/slos619/ slos619.pdf
[4] M. A. Teplechuk et al., True filterless class-D audio amplifier, IEEE J. Solid-State
Circuits, vol. 46, no. 12, pp. 27842793, Dec. 2011
[5] Oliver TresCases, et al. Prefictive Efficiency Optimization for DC-DC Converters With
Highly Dynamic Digital Logic IEEE, Power Electronics, Vol. 23, No. 4 July 2008
[6] Wei Shu and Joseph S. Chang THD of Closed-Loop Analog PWM Class-D Amplifier
IEEE transactions on circuits and Systems-I: Regular Papers, Vol. 55, no.6, July 2008
[7] Adrian I Colli-Menchi, Miguel A Rojas-Gonzalez, Edgar Sanchez-Sinencio Design Tech-
niques for Integrated CMOS Class-D Audio Amplifiers, Advanced Series in Electrical
and Computer Engineering: Volume 16
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