SlideShare a Scribd company logo
Multiprocessor Architecture
Asst. Prof. Vani Malagar
Contents
 Introduction to Multiprocessing Systems
 Types of Multiprocessing Systems
 Advantages of Multiprocessing
 Examples to Multiprocessors
 Interconnection Structures
Asst. Prof. Vani
Malagar
Introduction
 Multiprocessing is the use of two or more central processing units (CPUs) within a
single computer system. The term also refers to the ability of a system to support
more than one processor and/or the ability to allocate tasks between them.
 The term ‘processor’ in multiprocessor can mean either a CPU or an input-output
processor (IOP).
 There are some similarities between multiprocessor and multicomputer systems
since both support concurrent operations. However, there exists an important
distinction between the two.
 In case of multicomputer systems, several autonomous computers are connected
through a network that may or may not communicate with each other. On the
other hand, in a multiprocessor system, processors interact with each other
through an operating system and cooperate in the solution of a problem.
 Eg. Satellite Launching
Asst. Prof.
Vani
Asst. Prof. Vani Malagar
Asst. Prof.
Vani
Asst. Prof. Vani Malagar
Advantages of Multiprocessing
 A benefit derived from multiprocessing is improved system performance. This
happens because computations can proceed in parallel in one of two ways:-
a) Multiple independent jobs can be made to operate in parallel.
b) A single job can be partitioned into multiple parallel tasks.
 Increased Reliability: A failure or error in one part has a limited effect on the rest
of the system. If a fault causes one processor to fail, a second processor can be
assigned to perform the functions of the disabled processor.
 Increased Throughput: An increase in the number of processors completes the
work in less time. It is important to note that doubling the number of processors
does not halve the time to complete a job.
Asst. Prof.
Vani
Classification
Multiprocessors are classified by the way their memory is organized. There
are two main kinds of multiprocessing systems:-
 Tightly Coupled Systems (Common Shared Memory)
 Loosely Coupled Systems (Distributed Memory)
Asst. Prof.
Vani
Tightly Coupled Systems
 A multiprocessor system with common shared memory is classified as a shared-
memory or tightly coupled multiprocessor.
 This does not prevent each processor from having its own local memory.
 In fact, most commercial tightly coupled multiprocessors provide a cache memory
with each CPU. In addition, there is a global common memory that all CPUs can
access. Information can be therefore be shared among the CPUs by placing it in
the common global memory.
 Symmetric multiprocessing (SMP) involves a multiprocessor system architecture
where two or more identical processors connect to a single, shared main memory,
have full access to all I/O devices, and are controlled by a single operating system
instance that treats all processors equally, reserving none for special purposes.
Asst. Prof.
Vani
Diagram
Asst. Prof.
Vani
Loosely Coupled Systems
 An alternative model of microprocessor is the distributed memory or loosely
coupled system.
 Each processor element in a loosely coupled system has its own private local
memory.
 The processors are tied together by a switching scheme designed to route
information from one processor to another through a message-passing scheme.
 Loosely coupled systems are most efficient when the interaction between tasks is
minimal unlike tightly coupled systems can tolerate a higher degree of interaction
between tasks.
Asst. Prof.
Vani
Beowulf Cluster
The Borg, a 52-node Beowulf
cluster, is an example of a
loosely-coupled system. It is a
high-performance
computing cluster
parallel
from
inexpensive personal computer
hardware.
Asst. Prof.
Vani
Tightly & Loosely
Coupled Microprocessors
Asst. Prof.
Vani
Low coupling
CPU’s located at different Locations
No sharing of Buses , I/O devices etc
Efficient when tasks running on different processors has minimal interaction
between them (parallel applications).
No memory conflict occurs.
Processors communicate with each other by using message –passing.
Data Rate is low (becoz of different Location)
larger in size .
Scalability is high.
More Fault tolerant
Complex due to additional hardware is req.
Less portable
Asst. Prof.
Vani
Complete the Characteristics using the Tightly Coupled Microprocessor
Asst. Prof.
Vani
Types of Systems using the different Memory
organization :
UMA – (Tightly Coupled) –[Symmetric & Asymmetric]
NUMA – (Tightly Coupled )
COMA – (Loosely Coupled )
Asst. Prof.
Vani
UMA & NUMA
 Uniform memory access (UMA) is a shared memory architecture used in parallel
computers. All the processors in the UMA model share the physical memory
uniformly. The UMA model is suitable for general purpose and time sharing
applications by multiple users.
 Non-uniform memory access (NUMA) is a computer memory design used in
multiprocessing, where the memory access time depends on the memory location
relative to the processor. Under NUMA, a processor can access its own local
memory faster than non-local memory (memory local to another processor or
memory shared between processors).
Asst. Prof.
Vani
Asst. Prof.
Vani
UMA & NUMA
Asst. Prof.
Vani
Opteron
Opteron is AMD's x86 server and
workstation processor line, and was
the first processor which supported
the AMD64 instruction set
architecture (known generically as
x86-64).
The Opteron is a Non-Uniform
Memory Access (NUMA)
architecture.
Asst. Prof.
Vani
Asst. Prof.
Vani
Structure of Multiprocessor
Asst. Prof.
Vani
Interconnection Structures
Some of the physical forms available for establishing an interconnection
network between the components of a multiprocessor system are:
The collection of paths that connects the various modules such as CPU, I/O
processors ,Memory etc in order to communicate with each other is called
Interconnection structures.
Asst. Prof.
Vani
Physical Forms Includes :
 Time-shared common bus
 Multiport memory
 Crossbar switch
 Multistage switching Network
 Hypercube System
Asst. Prof.
Vani
Interconnection Topologies
Asst. Prof.
Vani
Time-Shared Common Bus
Memory
Unit
CPU 1 CPU 2 CPU 3 IOP 1 IOP 2
The main limitation of shared-bus multiprocessors is that the common bus tends to be the
primary source for contention, and thus imposes a limit on the number of processors in the
system. Alternative architectural features are necessary to reduce the memory bandwidth
demands and to increase the bus bandwidth.
Overcome by Cache Asst. Prof.
Vani
How to Overcome bus –
oriented Interconnection
Use of cache associated with each Processor.
Use of hierarchy of buses :
Local Bus
System Bus
Expansion Bus
.
Asst. Prof.
Vani
Asst. Prof.
Vani
Multiport Memory
MM 1 MM 2 MM 3 MM 4
CPU 1
CPU 2
CPU 3
CPU 4
14MCA0015Asst. Prof.
Vani
Cross Bar
Switch
Asst. Prof.
Vani
Crossbar Switch
MM 1 MM 2 MM 3 MM 4
CPU 1
CPU 2
CPU 3
CPU 4
Decrease
the cables
Asst. Prof.
Vani
Asst. Prof.
Vani
Asst. Prof.
Vani
Asst. Prof.
Vani
Multistage Switching
•Applied to build large Multiprocessor systems like Omege, Butterfly etc
•The switching Network can connect any Input to any Output by making appropriate
communication to each.
CPU
Memory
End’s
Switching
elements
Asst. Prof.
Vani
Asst. Prof.
Vani
Asst. Prof.
Vani
Hypercube
Asst. Prof.
Vani
Asst. Prof.
Vani
Asst. Prof.
Vani
Formulae:
N=8 ,then each node has direct
log (8)=3 other nodes connected
to it.
Hypercube composed of N=2^n
processor connected in an n-
dimensional binary cube.
E.g. N=1 then N=2^1=2
Processors
N=2 then N=2^2=4
Processors
Asst. Prof.
Vani
References
 Computer System Architecture, 3rd Edition by M. Morris Mano, Pearson Education
 Computer Architecture-A Quantitative Approach, 4th Edition by Hennessy and
Patterson
 http://en.wikipedia.org/wiki/Multiprocessing
 http://en.wikipedia.org/wiki/Symmetric_multiprocessing
Thank You! 
12/09/14 Arpan Baishya 14MCA0015 Asst. Prof.
Vani

More Related Content

What's hot

Amoeba distributed operating System
Amoeba distributed operating SystemAmoeba distributed operating System
Amoeba distributed operating System
Saurabh Gupta
 
Distributed & parallel system
Distributed & parallel systemDistributed & parallel system
Distributed & parallel systemManish Singh
 
Introduction to parallel processing
Introduction to parallel processingIntroduction to parallel processing
Introduction to parallel processing
Page Maker
 
Secondary storage management in os
Secondary storage management in osSecondary storage management in os
Secondary storage management in osSumant Diwakar
 
Multiprocessor structures
Multiprocessor structuresMultiprocessor structures
Multiprocessor structures
Shareb Ismaeel
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memory
Mazin Alwaaly
 
Distributed shred memory architecture
Distributed shred memory architectureDistributed shred memory architecture
Distributed shred memory architecture
Maulik Togadiya
 
Swap-space Management
Swap-space ManagementSwap-space Management
Swap-space Management
Agnas Jasmine
 
Distributed operating system(os)
Distributed operating system(os)Distributed operating system(os)
Distributed operating system(os)
Dinesh Modak
 
Computer architecture cache memory
Computer architecture cache memoryComputer architecture cache memory
Computer architecture cache memory
Mazin Alwaaly
 
Multiprocessor system
Multiprocessor system Multiprocessor system
Multiprocessor system
Mr. Vikram Singh Slathia
 
Multiprocessor
MultiprocessorMultiprocessor
Multiprocessor
Kamal Acharya
 
Heterogeneous computing
Heterogeneous computingHeterogeneous computing
Heterogeneous computing
Rashid Ansari
 
Distributed Operating System_1
Distributed Operating System_1Distributed Operating System_1
Distributed Operating System_1
Dr Sandeep Kumar Poonia
 
8. mutual exclusion in Distributed Operating Systems
8. mutual exclusion in Distributed Operating Systems8. mutual exclusion in Distributed Operating Systems
8. mutual exclusion in Distributed Operating Systems
Dr Sandeep Kumar Poonia
 
Multiprocessor
MultiprocessorMultiprocessor
Multiprocessor
Neel Patel
 
Distributed system
Distributed systemDistributed system
Distributed system
Syed Zaid Irshad
 
Shared Memory Multi Processor
Shared Memory Multi ProcessorShared Memory Multi Processor
Shared Memory Multi Processor
babuece
 
Centralized shared memory architectures
Centralized shared memory architecturesCentralized shared memory architectures
Centralized shared memory architectures
Gokuldhev mony
 
Computer architecture multi processor
Computer architecture multi processorComputer architecture multi processor
Computer architecture multi processor
Mazin Alwaaly
 

What's hot (20)

Amoeba distributed operating System
Amoeba distributed operating SystemAmoeba distributed operating System
Amoeba distributed operating System
 
Distributed & parallel system
Distributed & parallel systemDistributed & parallel system
Distributed & parallel system
 
Introduction to parallel processing
Introduction to parallel processingIntroduction to parallel processing
Introduction to parallel processing
 
Secondary storage management in os
Secondary storage management in osSecondary storage management in os
Secondary storage management in os
 
Multiprocessor structures
Multiprocessor structuresMultiprocessor structures
Multiprocessor structures
 
Computer architecture virtual memory
Computer architecture virtual memoryComputer architecture virtual memory
Computer architecture virtual memory
 
Distributed shred memory architecture
Distributed shred memory architectureDistributed shred memory architecture
Distributed shred memory architecture
 
Swap-space Management
Swap-space ManagementSwap-space Management
Swap-space Management
 
Distributed operating system(os)
Distributed operating system(os)Distributed operating system(os)
Distributed operating system(os)
 
Computer architecture cache memory
Computer architecture cache memoryComputer architecture cache memory
Computer architecture cache memory
 
Multiprocessor system
Multiprocessor system Multiprocessor system
Multiprocessor system
 
Multiprocessor
MultiprocessorMultiprocessor
Multiprocessor
 
Heterogeneous computing
Heterogeneous computingHeterogeneous computing
Heterogeneous computing
 
Distributed Operating System_1
Distributed Operating System_1Distributed Operating System_1
Distributed Operating System_1
 
8. mutual exclusion in Distributed Operating Systems
8. mutual exclusion in Distributed Operating Systems8. mutual exclusion in Distributed Operating Systems
8. mutual exclusion in Distributed Operating Systems
 
Multiprocessor
MultiprocessorMultiprocessor
Multiprocessor
 
Distributed system
Distributed systemDistributed system
Distributed system
 
Shared Memory Multi Processor
Shared Memory Multi ProcessorShared Memory Multi Processor
Shared Memory Multi Processor
 
Centralized shared memory architectures
Centralized shared memory architecturesCentralized shared memory architectures
Centralized shared memory architectures
 
Computer architecture multi processor
Computer architecture multi processorComputer architecture multi processor
Computer architecture multi processor
 

Similar to Multiprocessor Architecture (Advanced computer architecture)

Chapter 10
Chapter 10Chapter 10
Multiprocessor
Multiprocessor Multiprocessor
Multiprocessor
Irfan Khan
 
Lecture 6
Lecture  6Lecture  6
Lecture 6Mr SMAK
 
Lecture 6
Lecture  6Lecture  6
Lecture 6Mr SMAK
 
Lecture 6
Lecture  6Lecture  6
Lecture 6Mr SMAK
 
M7_L3_PPT.computer organization and archit
M7_L3_PPT.computer organization and architM7_L3_PPT.computer organization and archit
M7_L3_PPT.computer organization and archit
Sindhu Mani
 
Operating System Lecture 4
Operating System Lecture 4Operating System Lecture 4
Operating System Lecture 4
Dr. Ahmed J. Obaid
 
Multiprocessor Systems
Multiprocessor SystemsMultiprocessor Systems
Multiprocessor Systems
vampugani
 
Distributed Systems
Distributed SystemsDistributed Systems
Distributed Systems
vampugani
 
Parallel Processing.pptx
Parallel Processing.pptxParallel Processing.pptx
Parallel Processing.pptx
Sheethal Aji Mani
 
Distributed system notes unit I
Distributed system notes unit IDistributed system notes unit I
Distributed system notes unit I
NANDINI SHARMA
 
Multi processor
Multi processorMulti processor
Multi processor
Ibrahim Hassan
 
PARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTES
PARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTESPARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTES
PARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTES
suthi
 
Operating Systems
Operating SystemsOperating Systems
Operating Systems
achal02
 
ITM(2).ppt
ITM(2).pptITM(2).ppt
ITM(2).ppt
DimpyJindal4
 
OS UNIT1.pptx
OS UNIT1.pptxOS UNIT1.pptx
OS UNIT1.pptx
DHANABALSUBRAMANIAN
 
Symmetric multiprocessing and Microkernel
Symmetric multiprocessing and MicrokernelSymmetric multiprocessing and Microkernel
Symmetric multiprocessing and Microkernel
Manoraj Pannerselum
 
Unit 5 lect-3-multiprocessor
Unit 5 lect-3-multiprocessorUnit 5 lect-3-multiprocessor
Unit 5 lect-3-multiprocessor
vishal choudhary
 

Similar to Multiprocessor Architecture (Advanced computer architecture) (20)

Chapter 10
Chapter 10Chapter 10
Chapter 10
 
Multiprocessor
Multiprocessor Multiprocessor
Multiprocessor
 
Lecture 6
Lecture  6Lecture  6
Lecture 6
 
Lecture 6
Lecture  6Lecture  6
Lecture 6
 
Lecture 6
Lecture  6Lecture  6
Lecture 6
 
M7_L3_PPT.computer organization and archit
M7_L3_PPT.computer organization and architM7_L3_PPT.computer organization and archit
M7_L3_PPT.computer organization and archit
 
Operating System Lecture 4
Operating System Lecture 4Operating System Lecture 4
Operating System Lecture 4
 
Multiprocessor Systems
Multiprocessor SystemsMultiprocessor Systems
Multiprocessor Systems
 
Distributed Systems
Distributed SystemsDistributed Systems
Distributed Systems
 
Parallel Processing.pptx
Parallel Processing.pptxParallel Processing.pptx
Parallel Processing.pptx
 
Distributed system notes unit I
Distributed system notes unit IDistributed system notes unit I
Distributed system notes unit I
 
Multi processor
Multi processorMulti processor
Multi processor
 
PARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTES
PARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTESPARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTES
PARALLEL ARCHITECTURE AND COMPUTING - SHORT NOTES
 
Operating Systems
Operating SystemsOperating Systems
Operating Systems
 
ITM(2).ppt
ITM(2).pptITM(2).ppt
ITM(2).ppt
 
OS UNIT1.pptx
OS UNIT1.pptxOS UNIT1.pptx
OS UNIT1.pptx
 
Symmetric multiprocessing and Microkernel
Symmetric multiprocessing and MicrokernelSymmetric multiprocessing and Microkernel
Symmetric multiprocessing and Microkernel
 
Wiki 2
Wiki 2Wiki 2
Wiki 2
 
Week5
Week5Week5
Week5
 
Unit 5 lect-3-multiprocessor
Unit 5 lect-3-multiprocessorUnit 5 lect-3-multiprocessor
Unit 5 lect-3-multiprocessor
 

Recently uploaded

RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
thanhdowork
 
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTCHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT
jpsjournal1
 
[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf
[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf
[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf
awadeshbabu
 
Swimming pool mechanical components design.pptx
Swimming pool  mechanical components design.pptxSwimming pool  mechanical components design.pptx
Swimming pool mechanical components design.pptx
yokeleetan1
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
bakpo1
 
Ethernet Routing and switching chapter 1.ppt
Ethernet Routing and switching chapter 1.pptEthernet Routing and switching chapter 1.ppt
Ethernet Routing and switching chapter 1.ppt
azkamurat
 
Water billing management system project report.pdf
Water billing management system project report.pdfWater billing management system project report.pdf
Water billing management system project report.pdf
Kamal Acharya
 
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsKuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
Victor Morales
 
Low power architecture of logic gates using adiabatic techniques
Low power architecture of logic gates using adiabatic techniquesLow power architecture of logic gates using adiabatic techniques
Low power architecture of logic gates using adiabatic techniques
nooriasukmaningtyas
 
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
insn4465
 
Understanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine LearningUnderstanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine Learning
SUTEJAS
 
PPT on GRP pipes manufacturing and testing
PPT on GRP pipes manufacturing and testingPPT on GRP pipes manufacturing and testing
PPT on GRP pipes manufacturing and testing
anoopmanoharan2
 
Literature Review Basics and Understanding Reference Management.pptx
Literature Review Basics and Understanding Reference Management.pptxLiterature Review Basics and Understanding Reference Management.pptx
Literature Review Basics and Understanding Reference Management.pptx
Dr Ramhari Poudyal
 
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
ydteq
 
Modelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdfModelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdf
camseq
 
Tutorial for 16S rRNA Gene Analysis with QIIME2.pdf
Tutorial for 16S rRNA Gene Analysis with QIIME2.pdfTutorial for 16S rRNA Gene Analysis with QIIME2.pdf
Tutorial for 16S rRNA Gene Analysis with QIIME2.pdf
aqil azizi
 
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesHarnessing WebAssembly for Real-time Stateless Streaming Pipelines
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
Christina Lin
 
Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024
Massimo Talia
 
ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024
Rahul
 
6th International Conference on Machine Learning & Applications (CMLA 2024)
6th International Conference on Machine Learning & Applications (CMLA 2024)6th International Conference on Machine Learning & Applications (CMLA 2024)
6th International Conference on Machine Learning & Applications (CMLA 2024)
ClaraZara1
 

Recently uploaded (20)

RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
 
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTCHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT
 
[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf
[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf
[JPP-1] - (JEE 3.0) - Kinematics 1D - 14th May..pdf
 
Swimming pool mechanical components design.pptx
Swimming pool  mechanical components design.pptxSwimming pool  mechanical components design.pptx
Swimming pool mechanical components design.pptx
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
 
Ethernet Routing and switching chapter 1.ppt
Ethernet Routing and switching chapter 1.pptEthernet Routing and switching chapter 1.ppt
Ethernet Routing and switching chapter 1.ppt
 
Water billing management system project report.pdf
Water billing management system project report.pdfWater billing management system project report.pdf
Water billing management system project report.pdf
 
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsKuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
 
Low power architecture of logic gates using adiabatic techniques
Low power architecture of logic gates using adiabatic techniquesLow power architecture of logic gates using adiabatic techniques
Low power architecture of logic gates using adiabatic techniques
 
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
 
Understanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine LearningUnderstanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine Learning
 
PPT on GRP pipes manufacturing and testing
PPT on GRP pipes manufacturing and testingPPT on GRP pipes manufacturing and testing
PPT on GRP pipes manufacturing and testing
 
Literature Review Basics and Understanding Reference Management.pptx
Literature Review Basics and Understanding Reference Management.pptxLiterature Review Basics and Understanding Reference Management.pptx
Literature Review Basics and Understanding Reference Management.pptx
 
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
一比一原版(UofT毕业证)多伦多大学毕业证成绩单如何办理
 
Modelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdfModelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdf
 
Tutorial for 16S rRNA Gene Analysis with QIIME2.pdf
Tutorial for 16S rRNA Gene Analysis with QIIME2.pdfTutorial for 16S rRNA Gene Analysis with QIIME2.pdf
Tutorial for 16S rRNA Gene Analysis with QIIME2.pdf
 
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesHarnessing WebAssembly for Real-time Stateless Streaming Pipelines
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
 
Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024
 
ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024
 
6th International Conference on Machine Learning & Applications (CMLA 2024)
6th International Conference on Machine Learning & Applications (CMLA 2024)6th International Conference on Machine Learning & Applications (CMLA 2024)
6th International Conference on Machine Learning & Applications (CMLA 2024)
 

Multiprocessor Architecture (Advanced computer architecture)

  • 2. Contents  Introduction to Multiprocessing Systems  Types of Multiprocessing Systems  Advantages of Multiprocessing  Examples to Multiprocessors  Interconnection Structures Asst. Prof. Vani Malagar
  • 3. Introduction  Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them.  The term ‘processor’ in multiprocessor can mean either a CPU or an input-output processor (IOP).  There are some similarities between multiprocessor and multicomputer systems since both support concurrent operations. However, there exists an important distinction between the two.  In case of multicomputer systems, several autonomous computers are connected through a network that may or may not communicate with each other. On the other hand, in a multiprocessor system, processors interact with each other through an operating system and cooperate in the solution of a problem.  Eg. Satellite Launching Asst. Prof. Vani
  • 7. Advantages of Multiprocessing  A benefit derived from multiprocessing is improved system performance. This happens because computations can proceed in parallel in one of two ways:- a) Multiple independent jobs can be made to operate in parallel. b) A single job can be partitioned into multiple parallel tasks.  Increased Reliability: A failure or error in one part has a limited effect on the rest of the system. If a fault causes one processor to fail, a second processor can be assigned to perform the functions of the disabled processor.  Increased Throughput: An increase in the number of processors completes the work in less time. It is important to note that doubling the number of processors does not halve the time to complete a job. Asst. Prof. Vani
  • 8. Classification Multiprocessors are classified by the way their memory is organized. There are two main kinds of multiprocessing systems:-  Tightly Coupled Systems (Common Shared Memory)  Loosely Coupled Systems (Distributed Memory) Asst. Prof. Vani
  • 9. Tightly Coupled Systems  A multiprocessor system with common shared memory is classified as a shared- memory or tightly coupled multiprocessor.  This does not prevent each processor from having its own local memory.  In fact, most commercial tightly coupled multiprocessors provide a cache memory with each CPU. In addition, there is a global common memory that all CPUs can access. Information can be therefore be shared among the CPUs by placing it in the common global memory.  Symmetric multiprocessing (SMP) involves a multiprocessor system architecture where two or more identical processors connect to a single, shared main memory, have full access to all I/O devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Asst. Prof. Vani
  • 11. Loosely Coupled Systems  An alternative model of microprocessor is the distributed memory or loosely coupled system.  Each processor element in a loosely coupled system has its own private local memory.  The processors are tied together by a switching scheme designed to route information from one processor to another through a message-passing scheme.  Loosely coupled systems are most efficient when the interaction between tasks is minimal unlike tightly coupled systems can tolerate a higher degree of interaction between tasks. Asst. Prof. Vani
  • 12. Beowulf Cluster The Borg, a 52-node Beowulf cluster, is an example of a loosely-coupled system. It is a high-performance computing cluster parallel from inexpensive personal computer hardware. Asst. Prof. Vani
  • 13. Tightly & Loosely Coupled Microprocessors Asst. Prof. Vani
  • 14. Low coupling CPU’s located at different Locations No sharing of Buses , I/O devices etc Efficient when tasks running on different processors has minimal interaction between them (parallel applications). No memory conflict occurs. Processors communicate with each other by using message –passing. Data Rate is low (becoz of different Location) larger in size . Scalability is high. More Fault tolerant Complex due to additional hardware is req. Less portable Asst. Prof. Vani
  • 15. Complete the Characteristics using the Tightly Coupled Microprocessor Asst. Prof. Vani
  • 16. Types of Systems using the different Memory organization : UMA – (Tightly Coupled) –[Symmetric & Asymmetric] NUMA – (Tightly Coupled ) COMA – (Loosely Coupled ) Asst. Prof. Vani
  • 17. UMA & NUMA  Uniform memory access (UMA) is a shared memory architecture used in parallel computers. All the processors in the UMA model share the physical memory uniformly. The UMA model is suitable for general purpose and time sharing applications by multiple users.  Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors). Asst. Prof. Vani
  • 19. UMA & NUMA Asst. Prof. Vani
  • 20. Opteron Opteron is AMD's x86 server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture (known generically as x86-64). The Opteron is a Non-Uniform Memory Access (NUMA) architecture. Asst. Prof. Vani
  • 23. Interconnection Structures Some of the physical forms available for establishing an interconnection network between the components of a multiprocessor system are: The collection of paths that connects the various modules such as CPU, I/O processors ,Memory etc in order to communicate with each other is called Interconnection structures. Asst. Prof. Vani
  • 24. Physical Forms Includes :  Time-shared common bus  Multiport memory  Crossbar switch  Multistage switching Network  Hypercube System Asst. Prof. Vani
  • 26. Time-Shared Common Bus Memory Unit CPU 1 CPU 2 CPU 3 IOP 1 IOP 2 The main limitation of shared-bus multiprocessors is that the common bus tends to be the primary source for contention, and thus imposes a limit on the number of processors in the system. Alternative architectural features are necessary to reduce the memory bandwidth demands and to increase the bus bandwidth. Overcome by Cache Asst. Prof. Vani
  • 27. How to Overcome bus – oriented Interconnection Use of cache associated with each Processor. Use of hierarchy of buses : Local Bus System Bus Expansion Bus . Asst. Prof. Vani
  • 29. Multiport Memory MM 1 MM 2 MM 3 MM 4 CPU 1 CPU 2 CPU 3 CPU 4 14MCA0015Asst. Prof. Vani
  • 31. Crossbar Switch MM 1 MM 2 MM 3 MM 4 CPU 1 CPU 2 CPU 3 CPU 4 Decrease the cables Asst. Prof. Vani
  • 35. Multistage Switching •Applied to build large Multiprocessor systems like Omege, Butterfly etc •The switching Network can connect any Input to any Output by making appropriate communication to each. CPU Memory End’s Switching elements Asst. Prof. Vani
  • 41. Formulae: N=8 ,then each node has direct log (8)=3 other nodes connected to it. Hypercube composed of N=2^n processor connected in an n- dimensional binary cube. E.g. N=1 then N=2^1=2 Processors N=2 then N=2^2=4 Processors Asst. Prof. Vani
  • 42. References  Computer System Architecture, 3rd Edition by M. Morris Mano, Pearson Education  Computer Architecture-A Quantitative Approach, 4th Edition by Hennessy and Patterson  http://en.wikipedia.org/wiki/Multiprocessing  http://en.wikipedia.org/wiki/Symmetric_multiprocessing
  • 43. Thank You!  12/09/14 Arpan Baishya 14MCA0015 Asst. Prof. Vani