This document describes using an automatic test controller called the LE1200 to perform both boundary scan testing (BST) and in-circuit testing (ICT) on a PIC32 microcontroller-based development board. The LE1200 is connected to the board via ribbon cables and can interleave BST and ICT test patterns to thoroughly test the board and its connections. Sample test result files are shown, with faults correctly detected when a pin on the microcontroller is shorted to ground during testing.

1. Inter-Working
Boundary Scan Test (BST)
+
In Circuit Test (ICT)
on
PIC32 MPU Based
MCHP Explorer 16 DevBoard
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2. BST + ICT Features
• Built in Lorenzo Electronics LE1200 Automatic Test Controller,
a suite of test configuration, test program development, and test
execution programs are provided for testing complex PCBA.
• Tackling distinctive BST and ICT domains with ease allowing
user total control of test sequences interweaving those 2 test
technologies and achieving better test coverage.
• Combining BST and ICT can detect VLSI pins shorts as well as
trace opens to its peripherals such as connectors. Testing can be
done on all PCBA pins in parallel, using 100% digital signals.
This can reduce test time, lower test fixture costs, and increase
test quality.
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3. Inter-Working BST + ICT setup
• LE1200 connected to the device under test (DUT) via
ribbon cables, for demo purposes, in place of bed-of-nail
test fixture. A system board, which performs digital ICT
test functions, is placed below the test interface board.
JTAG controller is easily mounted on top of the interface
board. Complete LE1200 along with its DC power supply
can be placed inside a mid-sized test fixture.
• The 3 ribbon cables connecting LE1200 and DUT are 14-
wire JTAG cable, 20-wire 3.3v dc power cable, and 40-wire
ICT tester I/O pins.
URL for Microchip Explorer 16 Development Board User's Guide:
http://ww1.microchip.com/downloads/en/DeviceDoc/50001589b.pdf
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4. LE1200: Test Operation Basics
• 256 ICT tester pins. Each ICT tester pin is programmable as an
output pin or input pin, to be tested connecting to DUT input
pin or output pin respectively.
• LE1200 Utilizes the same JPAG port controller as that of
LE1201. Their BST test programs can be easily ported.
• User programmable test program is carried out by LE1200 to
perform test operations. It can be divided into multiple test
patterns. Each test pattern can be further classified into the
drive-signals and the expected received-signals.
• ICT and BST are driven by different control channels. For that,
their test operations cannot be mixed together within a test
pattern. However, their test patterns can be interleaving each
other as needed.
• ICT test pattern execution starts with applying drive-signals on
the ICT tester output pins, wait for DUT response for a specific
length of time, catch the DUT replies on the ICT tester input
pins, and validate those against the expected received-signals.
• Different from ICT, a BST test pattern specifies JTAG port's
tdi/tdo data streams associated with a JTAG TAP cycle
completing capture/shift/update operations. BST test pattern
designated drive-signals will be setup to a tdi data stream and
applied to the Binary Scan (BSC) IC pins at the end of test
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5. pattern. JTAG port tdo data stream will be validated against
BST test pattern expected received-signals. The tdo data
stream, however, can only reflect BSC IC pins logic states
before the BST test pattern is executed, not the immediate tdi
data stream.
• A test pattern sending a BST drive-signal can be validated by a
BST received-signal or an ICT input signal in the next test
pattern.
• A test pattern sending out ICT drive-signal can be validated by
the interconnected BSC IC pin in the next BST test pattern.
However, the associated BSC IC pin output cell must be
disabled (hi-Z) in earlier test pattern to avoid conflict.
• LE1200 is well suitable for testing modern PCBA loaded with
BST-capable VLSI. Those complex chips together with their
surrounding small logic chips and connectors can be tested with
the integrated BST and ICT tests. In most cases, expected
received-signals within a test pattern can be easily derived from
the drive-signals utilizing the test programming language
features.
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6. LE1200: ICT+BST Test Execution
• This test is divided into 2 parts, each covers different test
driving direction between BSC MPU and ICT pins. It started
with BST driving MPU pins and validated by both ICT and
MPU pins itself. Later, test directions will be reversed with
BST validating driving signals from ICT.
• MCHP Explorer 16 board's MPU pins with direct connection to
its PICtail connector J5 are selected for this test demo. They
are connected to ICT tester pins 65 → 71, and 153 → 160.
• Logical groups of MPU pins (or, its ports defined in BSDL) and
ICT tester pins are created to facilitate test programming. In
those groups, test patterns of single logic-1 bit are rippling
through all other logic-0's bits within the groups. Those test
patterns can easily detect both short-circuit faults and open-
circuit faults.
• Several test output trace files will be created. A sysout text file
lists high level test execution related info. For more detailed
test results, a sysout spreadsheet file listing all the test patterns,
displaying mainly ICT drive/received signals. Additionally,
BST tests will generate a spreadsheet file for each BSC device
detailing all BSC input/output/control cells information.
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7. snippet of sysout text file
• The sysout text file displays high level test execution system
information such as time stamps and test results. It also
illustrates BST JTAG port tdi/tdo bit streams contents in the
hexadecimal format.
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8. Snippet of a sysout spreadsheet file
• Spreadsheet columns B → H are displaying ICT tester pins 65
→ 71 logic states with defined signal names of RG6, RG7, ..
RD11. They are tested against MPU pins which have their
BSDL file defined port names of rg6, rg7, .. rd11 respectively.
For spreadsheet cells with contents of 0 or 1, they are ICT tester
driving logic levels, and those with L or H are ICT tester
detected logic levels.
• Spreadsheet columns L → S are displaying ICT tester pins 153
→ 160 logic states. Their ICT tester signals names d0 → d7 are
tested against MPU pins whose BSDL file defined port names
are re0 → re7, respectively.
• Test patterns 14, 16, …. are BST related. Their detailed test
patterns are listed in a separate spreadsheet file (P.9).
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9. Snippet of a BST device (u1) spreadsheet file
• Record detailed BSC output/ctrl cells driving logic states and
captured input cells logic states for the BST test patterns.
Notice that the test patterns skipped from this file are the ICT
test patterns listed in sysout spreadsheet file (P.8).
• Highlighted spreadsheet column DO records MPU pin 10 (port
name: RG6, BSC input cell #210) per test pattern captured
logic states (LE1200 conventions: H, L or X).
• Spreadsheet column DP shows MPU pin 10 (port name: RG6,
BSC output/ctrl cells, #211 and #212) per test pattern driving
logic states (LE1200 conventions: 0, 1, or Z). This MPU pin
will be tested against ICT tester pin #65 (signal name: RG6).
• This ICT+BST test passed. There is no “fail” label embedded
in either spreadsheet.
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10. ICT+BST Test Execution – Fault Inserted
• This fault insertion test demonstrates Lorenzo Electronics
LE1200 Automatic Test Controller fault detection capability
and the detailed data logs pointing to the defects.
• With MPU pin 10 shorted to GND, this ICT+BST test repeats
the same test program execution as that in page 6.
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11. snippet of sysout text file – Fault Inserted
• This sysout text file is indicating that test failed at test pattern
15 (ICT) and pattern 16 (BST, device: u1).
• TDO data stream in pattern 16 has indication that u1 pin 10 is
shorted to logic 0. The byte that contains BSC cell #210, with
hexadecimal value of 32 on the top row, has that cell's bit value
of 0. On page 7, in comparison, that byte's hexadecimal value
is 36. This verifies that this fault insertion test's TDO stream
has correctly pointing to the faulty BSC cell and ICT tester.
• Note: TDO mask bit stream with cell index #210 has the bit
value of 1. For that, the detected TDO data bit will be validated
against the expected test result.
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12. Snippet of a sysout spreadsheet file – Fault Inserted
• This sysout spreadsheet file column B records that ICT test
pattern 15 has detected logic L (and failed) in ICT tester pin 65
(signal name: RG6). Comparing to similar spreadsheet on page
8, the detected signal level is H in pattern #15.
• Two additional failed test patterns, #16 and #39, are detected in
BST. Details of BST failed information have to refer to BSC
device's spreadsheet file (P.13).
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13. Snippet of a BST device (u1) spreadsheet file – Fault Inserted
• This file lists explicitly BST test patterns. In the above snippet,
spreadsheet Column DO on test pattern #16 and #39 have
detected BSC IC pin 10 (port name: RG6, cell #210) logic level
L and failed. Comparing to similar spreadsheet on page 9, their
detected signal levels are H in those 2 test patterns.
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