The document discusses a low-power parallel Chien search architecture for BCH (Bose–Chaudhuri–Hocquenghem) codes, focusing on its two-step approach aimed at decreasing power consumption while maintaining efficient decoding throughput. It outlines the traditional BCH decoding blocks, identifies power challenges associated with the existing architecture, and presents the proposed model which leverages a pipelined structure to reduce access to the power-intensive second step. Experimental results demonstrate that this new architecture can achieve up to a 50% reduction in power consumption compared to conventional methods.

1. LOW POWER PARELLEL CHEIN SEARCH
ARCHITECTURE USING TWO STEP
APPROACH

2.  INTRODUCTION
 CHEIN SEARCH
 PROBLEM WITH EXISTING ARCHITECTURE
 PROPOSED SYSTEM
 OVERVIEW
 DECODER DESIGN AND ARCHITECTURE FOR BCH CODE
 ADVANTAGES
 APPLICATIONS
 CONCLUSION
 REFERANCES

3. •INTRODUCTION:
Among various error-correction codes used to recover corrupted code words in
communications and storage systems, the BCH code is one of the most widely
used algebraic codes due to its powerful error-correction performance and
affordable hardware complexity. The binary BCH code has been employed in
diverse systems such as advanced solid-state storages. In general, a BCH decoder
that can correct t bits at maximum is composed of three main blocks, namely,
syndrome calculation (SC), key-equation solving (KES), and Chien search (CS)
Given a received code word R(x), the SC computes 2tsyndromes, and the KES
generates the error locator polynomial Λ(x) using the syndromes. Finally, error
position E(x) is deter-mined by finding the roots of Λ(x) based on the CS
algorithm. In a parallel BCH decoder, the CS is a major contributor to the power
consumption and takes up to a half of overall power consumption.

4.  CHEIN SEARCH:
In abstract algebra, the Chien search, named after Robert Tienwen Chien, is a
fast algorithm for determining roots of polynomials defined over a finite field.
Chien search is commonly used to find the roots of error-locator polynomials
encountered in decoding Reed-Solomon codes and BCH codes.
The problem is to find the roots of the polynomial Λ(x) (over the finite
field GF(q)):

5. PROBLEM WITH EXISTING ARCHITECTURE:
Among various error-correction codes used to recover corrupted code words in
communications and storage systems, the Bose–Chaudhuri–Hocquenghem
(BCH) code , is one of the most widely used algebraic codes due to its powerful
error-correction performance and affordable hardware complexity. The binary
BCH code has been employed in diverse systems such as advanced solid-state
storages and optical fiber communication systems, and most of these
applications are continuously demanding ever higher decoding throughput and
ever larger error-correction capability. Since a massive computation is
inevitable in satisfying high throughput and strong error-correction capability,
power-efficient structure becomes more important in BCH decoding.

6. EXISTING BLOCK DIAGRAM:

7. PROPOSED SYSTEM:
We propose a new approach in which the parallel CS is decomposed into
two steps. The first step is accesse devery cycle, but the second step is
activated only when the first step is successful, resulting in a less number
of access. The proposed two-step approach is conceptually similar to that.
Although the two-step approach, in general, leads to the increase in
critical path delay and latency, the drawbacks areresolved in this brief by
employing an efficient pipelined structure. Unlike the previous
architectures, the proposed architecture can save the power consumption
regardless of error locations.

8. PROPOSED APPROACH:

9. OVERVIEW:
• In the present Digital Communication systems, it is highly possible that the data
or message get corrupted during transmission and reception through a noisy
channel medium. The environmental interference and the physical defects in the
medium are the main causes of the data or message corruption in the
communication medium, which leads to the injection of random bits into the
original message and corrupt the original message.
• Because of the addition of parity bits to message bits makes the size of the
original message bits longer. Now this longer message bits is called “Codeword”.
This codeword is received by the receiver at destination, and could be decoded to
retrieve the original message bits.

10. • The error correction is based on mathematical formulas, which are used by
Error correcting codes (ECC). Error correction is taken place by adding parity
bits to the original message bits during transmission of the data.
• There are many types of error correction codes are used in present digital
communication system are based on the type of errorexpected.
• Some of them are BCH, Turbo, Reed Solemon and LDPC.

11. DECODER DESIGN AND ARCHITECTURE FOR BCH
CODE:
Figure : High level decoder design
Where, R = Received data, S = Generated Syndromes, Λ =
Error locator polynomial

12. The BCH decoder has four modules as mentioned below:
• Syndrome Calculator
• Solving the key equation
• Error Location
• Error Correction
• Syndrome Calculator:
The syndrome calculator is the first module at the decoder also, the design of
this module is almost same for all the BCH code decoder architecture. The
input to this module is corrupted codeword. The equations for the codeword,
received bits and the error bits are given in equations
Codeword equation c(x) = c0 + c1x + c2x2 + ... + cn-1xn-1
Received bits equation r(x) = r0 + r1x + r2x2 + ... + rn-1xn-1
Error bits equation e(x) = e0 + e1x + e2x2 + ... + en-1xn-1

13. Thus, the final transmitted data polynomial equation is given as below:
r(x) = c(x) + e(x)
The 1st step at the decoding process is to store the transmitted data
polynomial in the buffer register and then to calculate the syndromes sj.

14. Fig : Conventional Syndrome Calculator
• Key Equation Solver:
The second stage in the decoding process is to find the co-efficient of the error
location polynomial using the generated syndromes in the previous stage. The error
location polynomial is given as: (x) = 0 + 1x + ... + txt. The relation between the
syndromes and the error location polynomial is given as below
St i j
j
t
j 

 
0
0 (i= 1, ..., t)
• There are various algorithms used to solve the key equation solver. This project is using
the Inversion less Berlekamp Massey algorithm to solve the key equation.

15. •Error Location – Chain’s Search:
To calculate the error location is the next step of decoding process, which can be
done using chain search block.
Chain Search Algorithm:
The roots are calculated as follows:
•For each power of α for ( j = 0 to n – 1), αj is taken as the test root
•Calculate the polynomial coefficients, of the current root using, coefficients of the
past iteration, using, Λ i
(j) = Λ i
(j-1) αi during the jth iteration
•Calculate the sum of the polynomial coefficients
•The sum is equal to
•Continue to Step 1 till j = n-1

16. Fig: Chain’s Search architecture – Error Location
• Error Correction:
The output of the chain search block is called roots of equation. The reciprocal of the
roots of equations are added with the corresponding location of the corrupted
codeword received by decoder. The result of this addition is the original codeword
that was encoded by the encoder before transmission.

17. ADVANTAGES:
• Affordable hardware complexity
• Delay reduced, Low Power, Less Area
• Higher Decoding throughput
• Larger error correction

18. APPLICATIONS:
• Digital Signal Processing
• Communication
• The BCH can be employed in diverse systems such as solid state
storage.

19. CONCLUSION:
This brief has presented a new low-power architecture for parallel CS. The
conventional CS is decomposed into two steps to achieve a significant power
saving by reducing access to the second step. Under the equally probable
error model, the low-power CS architecture is compared with the
conventional architecture for various configurations of field dimension,
parallel factor, and error-correction capability. Experimental results show that
the proposed architecture reduces up to 50% power consumption compared
with the conventional parallel CS.

20. Experimental results show that the proposed architecture reduces up to 50%
power consumption compared with the conventional parallel CS.The power
saving becomes more significant as the parallel factor or the field dimension
increases. The proposed two-step CS is also applicable to other linear block
codes such as the Reed–Solomon codes.

22. REFERENCES:
• S. Lin and D. J. Costello, Error Control Coding: Fundamentals and
Applications, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.
•S. B. Wicker, Error Control Systems for Digital Communication and Storage.
Englewood Cliffs, NJ, USA: Prentice-Hall, 1994.
•Y. Lin, C. Yang, C. Hsu, H. Chang, and C. Lee, “A MPCN-based parallel
architecture in BCH decoders for NAND Flash memory devices,” IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 58, no. 10, pp. 682–686, Oct. 2011.
•Y. Lee, H. Yoo, and I.-C. Park, “High-throughput and low-complexity BCH
decoding architecture for solid-state drives,” IEEE Trans. Very LargeScale Integr.
Syst., vol. 22, no. 5, pp. 1183–1187, May 2014.
•X. Zhang and Z. Wang, “A low-complexity three-error-correcting BCH decoder
for optical transport network,” IEEE Trans. Circuits Syst. II, Exp.Briefs.

23. THANK YOU