The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
Performance analysis of transmission of 5 users based on model b using gf (5)...csandit
We present transmission of five users with 5 WDM × 4 TDM × 5 CODE channel on 3D
OCDMA system based on Model B using GF (5) with varying receiver attenuation at 1Gbps, 2
Gbps, 5Gbps and 10Gbps data rates on OPTSIM.
A new efficient way based on special stabilizer multiplier permutations to at...IJECEIAES
BCH codes represent an important class of cyclic error-correcting codes; their minimum distances are known only for some cases and remains an open NP-Hard problem in coding theory especially for large lengths. This paper presents an efficient scheme ZSSMP (Zimmermann Special Stabilizer Multiplier Permutation) to find the true value of the minimum distance for many large BCH codes. The proposed method consists in searching a codeword having the minimum weight by Zimmermann algorithm in the sub codes fixed by special stabilizer multiplier permutations. These few sub codes had very small dimensions compared to the dimension of the considered code itself and therefore the search of a codeword of global minimum weight is simplified in terms of run time complexity. ZSSMP is validated on all BCH codes of length 255 for which it gives the exact value of the minimum distance. For BCH codes of length 511, the proposed technique passes considerably the famous known powerful scheme of Canteaut and Chabaud used to attack the public-key cryptosystems based on codes. ZSSMP is very rapid and allows catching the smallest weight codewords in few seconds. By exploiting the efficiency and the quickness of ZSSMP, the true minimum distances and consequently the error correcting capability of all the set of 165 BCH codes of length up to 1023 are determined except the two cases of the BCH(511,148) and BCH(511,259) codes. The comparison of ZSSMP with other powerful methods proves its quality for attacking the hardness of minimum weight search problem at least for the codes studied in this paper.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Performance Study of RS (255, 239) and RS (255.233) Used Respectively in DVB-...IJERA Editor
The error correction codes have a wide range of applications in digital communication (satellite, wireless) and digital data storage. This paper presents a comparative study of performance between RS (255, 239) and RS (255.233) used respectively in the Digital Video Broadcasting – Terrestrial (DVB-T) and National Aeronautics and Space Administration (NASA). The performances were evaluated by applying modulation scheme in additive white Gaussian noise (AWGN) channel. Performances of modulation with RS codes are evaluated in bit error rate (BER) and signal energy -to- noise power density ratio (Eb / No). The analysis is studied with the help of MATLAB simulator to analyze a communication link with AWGN Channel, and different modulations.
Performance analysis of transmission of 5 users based on model b using gf (5)...csandit
We present transmission of five users with 5 WDM × 4 TDM × 5 CODE channel on 3D
OCDMA system based on Model B using GF (5) with varying receiver attenuation at 1Gbps, 2
Gbps, 5Gbps and 10Gbps data rates on OPTSIM.
A new efficient way based on special stabilizer multiplier permutations to at...IJECEIAES
BCH codes represent an important class of cyclic error-correcting codes; their minimum distances are known only for some cases and remains an open NP-Hard problem in coding theory especially for large lengths. This paper presents an efficient scheme ZSSMP (Zimmermann Special Stabilizer Multiplier Permutation) to find the true value of the minimum distance for many large BCH codes. The proposed method consists in searching a codeword having the minimum weight by Zimmermann algorithm in the sub codes fixed by special stabilizer multiplier permutations. These few sub codes had very small dimensions compared to the dimension of the considered code itself and therefore the search of a codeword of global minimum weight is simplified in terms of run time complexity. ZSSMP is validated on all BCH codes of length 255 for which it gives the exact value of the minimum distance. For BCH codes of length 511, the proposed technique passes considerably the famous known powerful scheme of Canteaut and Chabaud used to attack the public-key cryptosystems based on codes. ZSSMP is very rapid and allows catching the smallest weight codewords in few seconds. By exploiting the efficiency and the quickness of ZSSMP, the true minimum distances and consequently the error correcting capability of all the set of 165 BCH codes of length up to 1023 are determined except the two cases of the BCH(511,148) and BCH(511,259) codes. The comparison of ZSSMP with other powerful methods proves its quality for attacking the hardness of minimum weight search problem at least for the codes studied in this paper.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Design and Performance Analysis of Convolutional Encoder and Viterbi Decoder ...IJERA Editor
In digital communication forward error correction methods have a great practical importance when channel is
noisy. Convolutional error correction code can correct both type of errors random and burst. Convolution
encoding has been used in digital communication systems including deep space communication and wireless
communication. The error correction capability of convolutional code depends on code rate and constraint
length. The low code rate and high constraint length has more error correction capabilities but that also
introduce large overhead. This paper introduces convolutional encoders for various constraint lengths. By
increasing the constraint length the error correction capability can be increased. The performance and error
correction also depends on the selection of generator polynomial. This paper also introduces a good generator
polynomial which has high performance and error correction capabilities.
Fpga implementation of linear ldpc encodereSAT Journals
Abstract In this paper, a FPGA implementation of linear time LDPC encoder is presented. This encoder implementation can handle large size of input message. Linear Time encoder hardware architecture reduces the Complexity and area of encoder than generator matrix based encoder techniques. This encoder is simulated on different platform which includes Matlab & High level languages for 1/2 rate & up to 4096 code length. FPGA implementation of the encoder is done on Xilinx Spartan 3E Starter Kit. The result shows the speed & area comparison for different FPGA platform. Keywords— LDPC codes, dual-diagonal, Linear encoding, Generator matrix complexity, FPGA Implementation
Reliability Level List Based Iterative SISO Decoding Algorithm for Block Turb...TELKOMNIKA JOURNAL
An iterative Reliability Level List (RLL) based soft-input soft-output (SISO) decoding algorithm has been proposed for Block Turbo Codes (BTCs). The algorithm ingeniously adapts the RLL based decoding algorithm for the constituent block codes, which is a soft-input hard-output algorithm. The extrinsic information is calculated using the reliability of these hard-output decisions and is passed as soft-input to the iterative turbo decoding process. RLL based decoding of constituent codes estimate the optimal transmitted codeword through a directed minimal search. The proposed RLL based decoder for the constituent code replaces the Chase-2 based constituent decoder in the conventional SISO scheme. Simulation results show that the proposed algorithm has a clear advantage of performance improvement over conventional Chase-2 based SISO decoding scheme with reduced decoding latency at lower noise levels.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Error control coding using bose chaudhuri hocquenghem bch codesIAEME Publication
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Analysis of LDPC Codes under Wi-Max IEEE 802.16eIJERD Editor
The LDPC codes have been shown to be by-far the best coding scheme capable for transmitting message over noisy channel. The main aim of this paper is to study the behaviour of LDPC codes on under IEEE 802.16e guidelines. The rate- ½ LDPC codes have been implemented on AWGN channel and the result shows that they can be used on such channels with low BER performance. The BER can be further minimized by increasing the block length.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
Low Power FPGA Based Elliptical Curve CryptographyIOSR Journals
Cryptography is the study of techniques for ensuring the secrecy and authentication of the
information. The development of public-key cryptography is the greatest and perhaps the only true revolution in
the entire history of cryptography. Elliptic Curve Cryptography is one of the public-key cryptosystem showing
up in standardization efforts, including the IEEE P1363 Standard. The principal attraction of elliptic curve
cryptography compared to RSA is that it offers equal security for a smaller key-size, thereby reducing the
processing overhead. As a Public-Key Cryptosystem, ECC has many advantages such as fast speed, high
security and short key. It is suitable for the hardware of implementation, so ECC has been more and more
focused in recent years. The hardware implementation of ECC on FPGA uses the arithmetic unit that has small
area, small storage unit and fast speed, and it is an extremely suitable system which has limited computation
ability and storage space.[1][2] The modular arithmetic division operations are carried out using conditional
successive subtractions, thereby reducing the area. The system is implemented on Vertex-Pro XCV1000 FPGA
Study of Microbial Pollution in River Beehar Water District Rewa Madhya Prade...IJERA Editor
Water is one of the best gifts to all living creature, given by nature. It is compulsory for the growth and maintenance of human body and also for many biological activities. It plays a vital role for the survival of all forms of life of earth and works as a universal solvent. Pollution is caused when a change in the physical, chemical or biological condition in the environment harmfully affect quality of human life including other animal’s life and plant The quality of water is typically determined by monitoring microbial presence, especially total coliforms, fecal coliforms and fecal streptococci. The total coliform count varied in the range of 836-1987.43 MPN/100 ml, 743-981 MPN/100ml, 1115.4 to 2010 MPN/100 ml; fecal coliform varied in the range of 763-1947.61 MPN/100 ml, 547-979 MPN/100 ml and 1057 to 1378 MPN/100 ml and fecal streptococci varied in the range of 881-1969.53 and 832.63-1098.86 MPN/100 ml, 1155 to 1512 MPN/100 ml during winter, summer and rainy season, respectively.
Efficient production of negative hydrogen ions in RF plasma by using a self-b...IJERA Editor
Volume production of negative hydrogen ions is established efficiently in a pure hydrogen RF discharge plasma by using a self-biased grid electrode for production of low electron-temperature and high density plasma. Using this electrode both high and low electron temperature plasmas are produced in the regions separated by the grid electrode in the chamber, in which the electron temperature in the downstream region is controlled by the mesh size and plasma production parameters. The production rate of negative ions depends strongly on the electron temperature varied by the RF input power and hydrogen pressure. In the case of the grid electrode with the 5 mesh/in., the negative hydrogen ions are produced effectively in the downstream region in the hydrogen pressure range of 0.9 −2.7 Pa. In addition, the production rate of the negative ion 퐻 − raises from 62 % to 87 % at 0.9 Pa by changing the RF power from 20 W to 80W.
Logo Matching for Document Image Retrieval Using SIFT DescriptorsIJERA Editor
In current trends the logos are playing a vital role in industrial and all commercial applications. Fundamentally the logo is defined as it’s a graphic entity which contains colors textures, shapes and text etc., which is organized in some special visible format. But unfortunately it is very difficult thing to save their brand logos from duplicates. In practical world there are several systems available for logo reorganization and detection with different kinds of requirements. Two dimensional global descriptors are used for logo matching and reorganization. The concept of Shape descriptors based on Shape context and the global descriptors are based on the logo contours. There is an algorithm which is implemented for logo detection is based on partial spatial context and spatial spectral saliency (SSS). The SSS is able to keep away from the confusion effect of background and also speed up the process of logo detection. All such methods are useful only when the logo is visible completely without noise and not subjected to change. We contribute, through this paper, to the design of a novel variation framework able to match and recognize multiple instances of multiple reference logos in image archives. Reference logos and test images are seen as constellations of local features (interest points, regions, etc.) and matched by minimizing an energy function mixing: 1) a fidelity term that measures the quality of feature matching, 2) a neighborhood criterion that captures feature co-occurrence geometry, and 3) a regularization term that controls the smoothness of the matching solution. We also introduce a detection/recognition procedure and study its theoretical consistency
Kinetics and Mechanism of the Reaction of Coherently Synchronized Oxidation a...IJERA Editor
Inducing effect of hydrogen peroxide on synchronous oxidation reaction is accompanied by the occurrence of two interconnected and interacting reactions. The reaction of Н2О2 decomposition (primary) generates the leading active OH and HO 2 free radicals in a system. During the interaction of active and free radicals with the substrate, the conversion of the substrate occurs in the secondary reaction, coherently-synchronized with the primary one. The mechanism of such coherently synchronized reactions is being examined in the process of cyclohexane oxidation with hydrogen peroxide in homogeneous and heterogeneous systems. The process of coupling dehydrogenation of cyclohexane to cyclohexene and cyclohexadiene with hydrogen peroxide was carried out without catalyst. This process was also carried out at a fairly low temperature in a heterogeneous catalytic system. Biomimetic catalyst, which simulates the basic functions of the enzyme group of oxidoreductase - catalase and monooxygenase, was used as the catalyst here. Characterised by its highly active and selective action these biomimetic catalysts are synthesized based on iron-porphyrin complexes simulating the active component of cytochrome P-450. Based on this experimental researches, the complex reaction, consisting of parallel-sequential oxidation and dehydrogenation reactions, which are coherently synchronized, proceeds during the process of cyclohexane oxidation with biomimetic catalyst. Depending on the reaction parameters it is possible to deliberately adjust the direction of oxidation reaction and reaction rate.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Design and Performance Analysis of Convolutional Encoder and Viterbi Decoder ...IJERA Editor
In digital communication forward error correction methods have a great practical importance when channel is
noisy. Convolutional error correction code can correct both type of errors random and burst. Convolution
encoding has been used in digital communication systems including deep space communication and wireless
communication. The error correction capability of convolutional code depends on code rate and constraint
length. The low code rate and high constraint length has more error correction capabilities but that also
introduce large overhead. This paper introduces convolutional encoders for various constraint lengths. By
increasing the constraint length the error correction capability can be increased. The performance and error
correction also depends on the selection of generator polynomial. This paper also introduces a good generator
polynomial which has high performance and error correction capabilities.
Fpga implementation of linear ldpc encodereSAT Journals
Abstract In this paper, a FPGA implementation of linear time LDPC encoder is presented. This encoder implementation can handle large size of input message. Linear Time encoder hardware architecture reduces the Complexity and area of encoder than generator matrix based encoder techniques. This encoder is simulated on different platform which includes Matlab & High level languages for 1/2 rate & up to 4096 code length. FPGA implementation of the encoder is done on Xilinx Spartan 3E Starter Kit. The result shows the speed & area comparison for different FPGA platform. Keywords— LDPC codes, dual-diagonal, Linear encoding, Generator matrix complexity, FPGA Implementation
Reliability Level List Based Iterative SISO Decoding Algorithm for Block Turb...TELKOMNIKA JOURNAL
An iterative Reliability Level List (RLL) based soft-input soft-output (SISO) decoding algorithm has been proposed for Block Turbo Codes (BTCs). The algorithm ingeniously adapts the RLL based decoding algorithm for the constituent block codes, which is a soft-input hard-output algorithm. The extrinsic information is calculated using the reliability of these hard-output decisions and is passed as soft-input to the iterative turbo decoding process. RLL based decoding of constituent codes estimate the optimal transmitted codeword through a directed minimal search. The proposed RLL based decoder for the constituent code replaces the Chase-2 based constituent decoder in the conventional SISO scheme. Simulation results show that the proposed algorithm has a clear advantage of performance improvement over conventional Chase-2 based SISO decoding scheme with reduced decoding latency at lower noise levels.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Error control coding using bose chaudhuri hocquenghem bch codesIAEME Publication
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Analysis of LDPC Codes under Wi-Max IEEE 802.16eIJERD Editor
The LDPC codes have been shown to be by-far the best coding scheme capable for transmitting message over noisy channel. The main aim of this paper is to study the behaviour of LDPC codes on under IEEE 802.16e guidelines. The rate- ½ LDPC codes have been implemented on AWGN channel and the result shows that they can be used on such channels with low BER performance. The BER can be further minimized by increasing the block length.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
Low Power FPGA Based Elliptical Curve CryptographyIOSR Journals
Cryptography is the study of techniques for ensuring the secrecy and authentication of the
information. The development of public-key cryptography is the greatest and perhaps the only true revolution in
the entire history of cryptography. Elliptic Curve Cryptography is one of the public-key cryptosystem showing
up in standardization efforts, including the IEEE P1363 Standard. The principal attraction of elliptic curve
cryptography compared to RSA is that it offers equal security for a smaller key-size, thereby reducing the
processing overhead. As a Public-Key Cryptosystem, ECC has many advantages such as fast speed, high
security and short key. It is suitable for the hardware of implementation, so ECC has been more and more
focused in recent years. The hardware implementation of ECC on FPGA uses the arithmetic unit that has small
area, small storage unit and fast speed, and it is an extremely suitable system which has limited computation
ability and storage space.[1][2] The modular arithmetic division operations are carried out using conditional
successive subtractions, thereby reducing the area. The system is implemented on Vertex-Pro XCV1000 FPGA
Study of Microbial Pollution in River Beehar Water District Rewa Madhya Prade...IJERA Editor
Water is one of the best gifts to all living creature, given by nature. It is compulsory for the growth and maintenance of human body and also for many biological activities. It plays a vital role for the survival of all forms of life of earth and works as a universal solvent. Pollution is caused when a change in the physical, chemical or biological condition in the environment harmfully affect quality of human life including other animal’s life and plant The quality of water is typically determined by monitoring microbial presence, especially total coliforms, fecal coliforms and fecal streptococci. The total coliform count varied in the range of 836-1987.43 MPN/100 ml, 743-981 MPN/100ml, 1115.4 to 2010 MPN/100 ml; fecal coliform varied in the range of 763-1947.61 MPN/100 ml, 547-979 MPN/100 ml and 1057 to 1378 MPN/100 ml and fecal streptococci varied in the range of 881-1969.53 and 832.63-1098.86 MPN/100 ml, 1155 to 1512 MPN/100 ml during winter, summer and rainy season, respectively.
Efficient production of negative hydrogen ions in RF plasma by using a self-b...IJERA Editor
Volume production of negative hydrogen ions is established efficiently in a pure hydrogen RF discharge plasma by using a self-biased grid electrode for production of low electron-temperature and high density plasma. Using this electrode both high and low electron temperature plasmas are produced in the regions separated by the grid electrode in the chamber, in which the electron temperature in the downstream region is controlled by the mesh size and plasma production parameters. The production rate of negative ions depends strongly on the electron temperature varied by the RF input power and hydrogen pressure. In the case of the grid electrode with the 5 mesh/in., the negative hydrogen ions are produced effectively in the downstream region in the hydrogen pressure range of 0.9 −2.7 Pa. In addition, the production rate of the negative ion 퐻 − raises from 62 % to 87 % at 0.9 Pa by changing the RF power from 20 W to 80W.
Logo Matching for Document Image Retrieval Using SIFT DescriptorsIJERA Editor
In current trends the logos are playing a vital role in industrial and all commercial applications. Fundamentally the logo is defined as it’s a graphic entity which contains colors textures, shapes and text etc., which is organized in some special visible format. But unfortunately it is very difficult thing to save their brand logos from duplicates. In practical world there are several systems available for logo reorganization and detection with different kinds of requirements. Two dimensional global descriptors are used for logo matching and reorganization. The concept of Shape descriptors based on Shape context and the global descriptors are based on the logo contours. There is an algorithm which is implemented for logo detection is based on partial spatial context and spatial spectral saliency (SSS). The SSS is able to keep away from the confusion effect of background and also speed up the process of logo detection. All such methods are useful only when the logo is visible completely without noise and not subjected to change. We contribute, through this paper, to the design of a novel variation framework able to match and recognize multiple instances of multiple reference logos in image archives. Reference logos and test images are seen as constellations of local features (interest points, regions, etc.) and matched by minimizing an energy function mixing: 1) a fidelity term that measures the quality of feature matching, 2) a neighborhood criterion that captures feature co-occurrence geometry, and 3) a regularization term that controls the smoothness of the matching solution. We also introduce a detection/recognition procedure and study its theoretical consistency
Kinetics and Mechanism of the Reaction of Coherently Synchronized Oxidation a...IJERA Editor
Inducing effect of hydrogen peroxide on synchronous oxidation reaction is accompanied by the occurrence of two interconnected and interacting reactions. The reaction of Н2О2 decomposition (primary) generates the leading active OH and HO 2 free radicals in a system. During the interaction of active and free radicals with the substrate, the conversion of the substrate occurs in the secondary reaction, coherently-synchronized with the primary one. The mechanism of such coherently synchronized reactions is being examined in the process of cyclohexane oxidation with hydrogen peroxide in homogeneous and heterogeneous systems. The process of coupling dehydrogenation of cyclohexane to cyclohexene and cyclohexadiene with hydrogen peroxide was carried out without catalyst. This process was also carried out at a fairly low temperature in a heterogeneous catalytic system. Biomimetic catalyst, which simulates the basic functions of the enzyme group of oxidoreductase - catalase and monooxygenase, was used as the catalyst here. Characterised by its highly active and selective action these biomimetic catalysts are synthesized based on iron-porphyrin complexes simulating the active component of cytochrome P-450. Based on this experimental researches, the complex reaction, consisting of parallel-sequential oxidation and dehydrogenation reactions, which are coherently synchronized, proceeds during the process of cyclohexane oxidation with biomimetic catalyst. Depending on the reaction parameters it is possible to deliberately adjust the direction of oxidation reaction and reaction rate.
Hardware implementation of (63, 51) bch encoder and decoder for wban using lf...ijitjournal
Error Correcting Codes are required to have a reliable communication through a medium that has an
unacceptable bit error rate and low signal to noise ratio. In IEEE 802.15.6 2.4GHz Wireless Body Area
Network (WBAN), data gets corrupted during the transmission and reception due to noises and
interferences. Ultra low power operation is crucial to prolong the life of implantable devices. Hence simple
block codes like BCH (63, 51, 2) can be employed in the transceiver design of 802.15.6 Narrowband PHY.
In this paper, implementation of BCH (63, 51, t = 2) Encoder and Decoder using VHDL is discussed. The
incoming 51 bits are encoded into 63 bit code word using (63, 51) BCH encoder. It can detect and correct
up to 2 random errors. The design of an encoder is implemented using Linear Feed Back Shift Register
(LFSR) for polynomial division and the decoder design is based on syndrome calculator, inversion-less
Berlekamp-Massey algorithm (BMA) and Chien search algorithm. Synthesis and simulation were carried
out using Xilinx ISE 14.2 and ModelSim 10.1c. The codes are implemented over Virtex 4 FPGA device and
tested on DN8000K10PCIE Logic Emulation Board. To the best of our knowledge, it is the first time an
implementation of (63, 51) BCH encoder and decoder carried out.
BCH Decoder Implemented On CMOS/Nano Device Digital Memories for Fault Tolera...inventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
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Targeting on the future fault-prone hybrid CMOS/Nanodevice digital memories, this paper present two faulttolerance
design approaches the integrally address the tolerance for defect and transient faults. These two
approaches share several key features, including the use of a group of Bose-Chaudhuri- Hocquenghem (BCH)
codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic
logical-to-physical address mapping. Thus, a new model of BCH decoder is proposed to reduce the area and
simplify the computational scheduling of both syndrome and chien search blocks without parallelism leading to
high throughput.The goal of fault tolerant computing is improve the dependability of systems where
dependability can be defined as the ability of a system to deliver service at an acceptable level of confidence in
either presence or absence falult.ss The results of the simulation and implementation using Xilinx ISE software
and the LCD screen on the FPGA’s Board will be shown at last.
An Efficient Interpolation-Based Chase BCH Decoderijsrd.com
Error correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. Bose,Ray Chaudhuri, Hocquenghem (BCH)codes are one of the error correcting codes. The BCH decoder consists of four blocks namely syndrome block, chien search block and error correction block. This paper describes a new method for error detection in syndrome and chien search block of BCH decoder. The proposed syndrome block is used to reduce the number of computation by calculating the even number syndromes from the corresponding odd number syndromes.
Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
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Conception of a new Syndrome Block for BCH codes with hardware Implementation...IJERA Editor
Error Correcting Codes are required to have a reliable communication through a medium that has an unacceptable bit error rate and low signal to noise ratio. Data gets corrupted during the transmission and reception due to noises and interferences. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are being widely used in variety communication and storage systems. In this paper, a simplified algorithm for BCH decoding is proposed with a view to reduce the number of iterations for error detection in the syndrome calculator block of BCH decoders with a percentage of up to 80 % compared to the basic syndrome block. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of syndrome block on FPGA card.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
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Low Power Parellel Chein Search Architecture using Two- Step ApproachMonalSarada
This brief proposes a new power-efficient Chien search (CS) architecture for parallel Bose-Chaudhuri-Hocquenghem (BCH) codes. In the proposed architecture, the searching process is decomposed into two steps based on the binary matrix representation. Unlike the first step accessed every cycle, the second step is activated only when the first step is successful, resulting in remarkable power saving.
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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...IOSR Journals
Abstract: In this paper we have designed and implemented(15, k) a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organized into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form up to k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 code word. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 13.3. BCH encoders are conventionally implemented by linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fan out, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. Also a comparative performance based on synthesis & simulation on FPGA is presented. Keywords: BCH, BCH Encoder, FPGA, VHDL, Error Correction, AWGN, LFSR cyclic redundancy checking, fan out .
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
n this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms.
Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers IJECEIAES
This paper presents the bit error rate performance of the low density parity check (LDPC) with the concatenation of convolutional channel coding based orthogonal frequency-division-multiplexing (OFDM) using space time block coded (STBC). The OFDM wireless communication system incorporates 3/4rated convolutional encoder under various digital modulations (BPSK, QPSK and QAM) over an additative white gaussian noise (AWGN) and fading (Raleigh and Rician) channels. At the receiving section of the simulated system, Maximum Ratio combining (MRC) channel equalization technique has been implemented to extract transmitted symbols without enhancing noise power.
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementationinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
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When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
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Performance Study of BCH Error Correcting Codes Using the Bit Error Rate Term BER
1. Elghayyaty Mohamed et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 2, ( Part -2) February 2017, pp.52-54
www.ijera.com DOI: 10.9790/9622- 0702025254 52 | P a g e
Performance Study of BCH Error Correcting Codes Using the Bit
Error Rate Term BER
Elghayyaty Mohamed1
, Hadjoudja Abdelkader2
, Omar Mouhib2
,
El Habti El IdrissiAnas2
, mahjoub chakir1
1
(Laboratory of the sciences of the engineer and modeling. Faculty of Sciences, University Ibn Tofail Kenitra,
Morocco)
2
(Laboratory of Electrical Engineering and Energy System. Faculty of Sciences, University Ibn Tofail Kenitra,
Morocco
ABSTRACT
The quality of a digital transmission is mainly dependent on the amount of errors introduced into the
transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication
systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This
paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15,
7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are
respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the
error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the
two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
Keywords: Bose-Chaudhuri-Hocquenghem codes, Math lab simulator, bit error rate, AWGN channel,
Performance
I. INTRODUCTION
Communication technologies are widely
used these days. Due to the growing percentage of
people using these technologies, methods are needed
to increase the transmission rate without reducing
the quality [1].Many digital signaling applications in
broadcasting use Forward Error Correction, a
technique in which redundant information is added
to the signal to allow the receiver to detect and
correct errors that may have occurred in
transmission. There are different types of error
correcting codes based on the type of error expected,
expected error rate of the communication medium,
and whether re-transmission is possible or not. Few
of them are BCH, Turbo, Reed Solomon, Hamming
and LDPC. These codes differ from each other in
their implementation and complexity[2]. In 1960s
Bose,Ray–Chaudhuri, Hocquenghem, independently
invented BCH codes. They are powerful class of
cyclic codes with multiple errors correcting
capability and well defined mathematical properties.
The Galois Field or Finite Field Theory defines the
mathematical properties of BCH codes [3]. The aim
of this work is to make a Comparative Performance
Analysis of Bose-Chaudhuri-Hocquenghem codes
BCH (15, 7, 2) and BCH (255, 231, 3) using the bit
error rate term (BER) and signal energy -to- noise
power density ratio (Eb / No). The rest of the paper
is organized as follows. Section II describes the
BCH encoder and illustrates the decoding process.
Section III presents a comparison study of
performances between BCH (15, 7, 2) and BCH
(255, 231, 3) using the bit error rate (BER). Finally,
the concluding remarks are given in Section IV.
II. BACKGROUND AND RELATED
WORK
2.1. BCH encoder
BCH (Bose – Chaudhuri - Hocquenghem)
Codes form a large class of multiple random error-
correcting codes.BCH Code is a generalized form of
Hamming Code. The possible BCH codes for m>=3
and t<2m-1 are:
Block length: n=2m-1
Parity check bits: n-k<=mt
Minimum distance: d>= 2t+1
Achieving the BCH codes is as follows:
1. Build the body of the Galois GF (qm)
Error correcting codes operate over a large
extent on powerful algebraic structures called finite
fields. A finite field is often known as Galois field
after Pierre Galois, the French mathematician. A
field is one in which addition, subtraction,
multiplication and division can be performed on the
field elements and thereby obtaining another element
within the set itself. A finite field always contains a
finite number of elements and it must be a prime
power, say q = pr, where p is prime. There exists a
field of order q for each prime power q = pr and it is
RESEARCH ARTICLE OPEN ACCESS
2. Elghayyaty Mohamed et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 2, ( Part -2) February 2017, pp.52-54
www.ijera.com DOI: 10.9790/9622- 0702025254 53 | P a g e
unique. In Galois field GF(q), the elements can take
this q different values.
We are exploiting the following properties of a finite
field:
a. Addition and multiplication operations are
defined.
b. The result of addition or multiplication of two
elements is always an element in the field.
c. Zero is an element in the field, such that a + 0 =
a for any element a in the field.
d. Unity is an element in the field, such that a • 1 =
a for any element a in the field.
2. Determine a primitive polynomial using the nth
root α in the Galois field GF (qm)
3. Choose 2t = γ -1 α consecutive power.
4. Build generator polynomial g (x) as the least
common multiple LCM of minimal polynomials
associated with the power to choose α.
2.2. BCH decoder
Three main steps for BCH decoding are represented
as follows [4]:
Step1: Computation of syndromes.
Step2: Berlekamp-Massey algorithm.
Step3: Detection of error position using Chien
Search Block.
a. Syndrome Block
The BCH code is characterized as (n, k, t),
where n is the code length, k is the data length, and t
is the error correction capability. The n-bit code
word ( ) can be interpreted as a
received polynomial [5], =
+ .In Syndrome
Calculation, 2t syndromes are computed using the
following equation:
= = =
+
The syndrome calculator block provides
two results. The first result is whether the received
code word is correct. The second result provides the
syndrome polynomial which will be used to correct
the code word if the code word is erroneous. The
most common algorithm to perform the syndrome
calculation needs 2t basic cells as defined in
Fig.1.Where 1 i≤2t.For each Syndrome Si, where
1 i≤ 2t, n iterations or computations are needed to
compute the Syndrome Polynomial. All the
syndrome coefficients will be equal to 0 if the
received code word is correct with at least one
coefficient different from 0 if the code word is not
correct [6].
Figure.1. Basic syndrome calculator cell
b. Berlekamp-Massey algorithm
Berlekamp-Massey algorithm consists of a
series of steps based on improving an approximation
to the error locator polynomial Ʌ (x) using a
correction polynomial C (x) and the Syndrome
values Si as inputs where: 1 i≤2t. It also requires a
step parameter K and a parameter L which tracks the
order of the equation.
c. Chien Search Block
This algorithm can detect the error position
by calculating Ʌ (α-i
) where 0 ≤ i ≤ n-1, such as Ʌ
(x) is the error locator polynomial, calculated with
the Euclidean algorithm defined in Fig.2. For the
case of RS (n, k) we must calculate:
Ʌ (α-(n-1)
), Ʌ (α-(n-2)
)… Ʌ (α-1
), Ʌ (α-0
)
If the expression reduces to 0, Ʌ (α-1
) = 0,
then that value of x is a root and identifies the error
position, else the position does not contain an error
[7].
Figure.2. Scheme of Chien Search Block
III. PERFORMANCE STUDY OF BCH
CODES
To analyze the performance using the bit
error rate term (BER) as shown in figure 3, two
codes are presented; BCH (15, 7, 2) and BCH (255,
231, 3). The channel and the modulation type are
respectively AWGN and PSK where the order of
modulation is equal to 2.
3. Elghayyaty Mohamed et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 2, ( Part -2) February 2017, pp.52-54
www.ijera.com DOI: 10.9790/9622- 0702025254 54 | P a g e
Fig.3. performance of BCH (15, 7, 2) and BCH
(255, 231, 3) codes using the bit error rate term
(BER)
The figure 3 shows the performance of two
codes: BCH (15, 7, 2) and BCH (255, 231, 3). One
of length 15, and the other of length 255, it is
observed that the coding gain is 1, 4 dB for a BER =
10-4
when the length of the code word changes from
15 to 255. However, when the code word length
increases, the complexity of calculating and
implementation increases too.
IV. CONCLUSION
In this paper, we have presented a
background and related work of the Bose-
Chaudhuri-Hocquenghem encoder and decoder. This
work is based on a simple comparison of codes BCH
(15, 7, 2) and BCH (255, 231, 3). This study
addressed the performance of BCH codes using the
bit error rate term (BER) and the noise power
density ratio of the signal energy (Eb / No).
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