This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
: Encryption is important to keep the confidentiality of data. There are many of encryption algorithms to ensure the data, but should be the select the algorithm depended on the fast, strong and implementation. For that choose the advance encryption standard (AES) algorithm for encryption data because speed and easy implementation on small devices and some the feature for it. In this paper, implementation of encryption and decryption of AES algorithm is presented with a High Secured Low Power Multiplexer Look-Up-Table (MLUT) based Substitution-Box (S-Box) . The main feature in the proposed MLUT based S-Box is that, it is implemented based on 256-byte to 1-byte multiplexer with a 256-byte memory instead of the conventional implementation of employing multiplication inversion in GF(28 ) and affine transformation. Thus, the proposed S-Box is simpler in circuit implementation and lower in power dissipation.
Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microbl...IJECEIAES
Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.
A design of a fast parallel pipelined implementation of aes advanced encrypti...ijcsit
The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a
sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is
a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design
of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use
pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on
combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different rounds, while the second is through
parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed
for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in
order to exploit the sources of parallelism in both initial and final round. This enhances the system
performance compared to previous designs. Using two-levels of parallelization benefits from the highly
independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The analysis shows that using
pipeline increases significantly the degree of improvement for both encryption and decryption by
approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column
transformations increases the degree of improvement by approximately 98%. This leads to the conclusion
that the proposed design is scalable and is suitable for real-time applications
A Cryptographic Hardware Revolution in Communication Systems using Verilog HDLidescitation
Advanced Encryption Standard (AES), is an
advancement of Federal Information Processing Standard
(FIPS) which is an initiated Process Standard of NIST. The
AES specifies the Rijndael algorithm, in which a symmetric
block cipher that processes fixed 128 bit data blocks using
cipher keys with different lengths of 128, 192 and 256 bits.
The earliest Rijndael algorithm had the advantage of
combining both data block sizes of 128, 192 and 256 bits with
any key lengths. AES can be programmed in pure hardware
Verilog HDL, Which includes Multiplexer to enhance more
secure to Cipher text. The results indicate that the hardware
implementation proposed in this project is Decrementing
Utilization of resource and power consumption of 113 mW
than other implementation. Using FPGA lead to reliability on
source modulations. This project presents the AES algorithm
with regard to FPGA and Verilog HDL. The software used for
Simulation is ModelSim-Altera 6.3g_p1 (Quartus II 8.1).
Synthesis and implementation of the code is carried out on
Xilinx ISE 13.4 (XC6VCX240T) device is used for hardware
evaluation.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
: Encryption is important to keep the confidentiality of data. There are many of encryption algorithms to ensure the data, but should be the select the algorithm depended on the fast, strong and implementation. For that choose the advance encryption standard (AES) algorithm for encryption data because speed and easy implementation on small devices and some the feature for it. In this paper, implementation of encryption and decryption of AES algorithm is presented with a High Secured Low Power Multiplexer Look-Up-Table (MLUT) based Substitution-Box (S-Box) . The main feature in the proposed MLUT based S-Box is that, it is implemented based on 256-byte to 1-byte multiplexer with a 256-byte memory instead of the conventional implementation of employing multiplication inversion in GF(28 ) and affine transformation. Thus, the proposed S-Box is simpler in circuit implementation and lower in power dissipation.
Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microbl...IJECEIAES
Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.
A design of a fast parallel pipelined implementation of aes advanced encrypti...ijcsit
The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a
sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is
a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design
of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use
pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on
combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different rounds, while the second is through
parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed
for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in
order to exploit the sources of parallelism in both initial and final round. This enhances the system
performance compared to previous designs. Using two-levels of parallelization benefits from the highly
independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The analysis shows that using
pipeline increases significantly the degree of improvement for both encryption and decryption by
approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column
transformations increases the degree of improvement by approximately 98%. This leads to the conclusion
that the proposed design is scalable and is suitable for real-time applications
A Cryptographic Hardware Revolution in Communication Systems using Verilog HDLidescitation
Advanced Encryption Standard (AES), is an
advancement of Federal Information Processing Standard
(FIPS) which is an initiated Process Standard of NIST. The
AES specifies the Rijndael algorithm, in which a symmetric
block cipher that processes fixed 128 bit data blocks using
cipher keys with different lengths of 128, 192 and 256 bits.
The earliest Rijndael algorithm had the advantage of
combining both data block sizes of 128, 192 and 256 bits with
any key lengths. AES can be programmed in pure hardware
Verilog HDL, Which includes Multiplexer to enhance more
secure to Cipher text. The results indicate that the hardware
implementation proposed in this project is Decrementing
Utilization of resource and power consumption of 113 mW
than other implementation. Using FPGA lead to reliability on
source modulations. This project presents the AES algorithm
with regard to FPGA and Verilog HDL. The software used for
Simulation is ModelSim-Altera 6.3g_p1 (Quartus II 8.1).
Synthesis and implementation of the code is carried out on
Xilinx ISE 13.4 (XC6VCX240T) device is used for hardware
evaluation.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
FPGA Implementation of an Area Optimized Architecture for 128 bit AES AlgorithmIJERA Editor
This paper aims at FPGA Implementation of an Area Optimized Architecture for 128 bit AES Algorithm. The
conventional designs use a separate module for 32 bit byte substitution and 128 bit byte substitution. The 32 bit
byte substitution is used in round key generation and the 128 bit byte substitution is used in the rounds. This
report presents a modified architecture of 128 bit byte substitution module using a single 32 bit byte substitution
module to reduce area.The AES encryption and decryption algorithm were designed using Verilog HDL. The
functionality of the modules were checked using ModelSim. The simulations were carried out in ModelSim and
Quartus II. The algorithm was implemented in FPGA and achieved a 2% reduction in the total logic element
utilization
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
High Speed VLSI Architecture for AES-Galois/Counter ModeIJERA Editor
Galois/Counter Mode of Operation (GCM) is a block cipher mode operation used to provide encryption and
authentication using universal Hashing based on multiplication over binary Galois/Finite Field.GCM can be
implemented on both hardware and software effectively and efficiently. GCM supports pipelined and
parallelized implementations to have minimal computational latency in order to be useful at high data rates.
However need for continual performance improvement is still presented due to continuous increase in network
bandwidth and inefficiency of existing parallelization methods. This paper presents use of modified parallel
GHASH module and modified key Expansion module to improve overall efficiency. GCM architecture is
modeled in Verilog HDL and Simulated in Xilinx ISE. ASIC implementation is done on 130 nm CMOS
technology. Test case 4 of NIST submission for Galois/Counter Mode (GCM) is also verified.
The importance of cryptography knuckle down to the security in electronic data transmissions has gained an essential relevance during past years. Cryptography security mechanisms uses some algorithms to muddle the data into unreadable text with a key which can only be decoded/decrypted by one who has that associated key for the locked data. Cryptography techniques are of two types: Symmetric & Asymmetric. In this paper we’ve used symmetric cryptography method-Advance Encryption Standard algorithm with 200 bit block size as well as 200 bit key size. We’ve used 5*5 matrix to implement same 128 bit conventional AES algorithm for 200 bit block size. After implementing the algorithm, the proposed work is compared with 128,192 & 256 bits AES techniques in context with Encryption and Decryption Time & Throughput at both Encryption and Decryption ends.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
FPGA Implementation of an Area Optimized Architecture for 128 bit AES AlgorithmIJERA Editor
This paper aims at FPGA Implementation of an Area Optimized Architecture for 128 bit AES Algorithm. The
conventional designs use a separate module for 32 bit byte substitution and 128 bit byte substitution. The 32 bit
byte substitution is used in round key generation and the 128 bit byte substitution is used in the rounds. This
report presents a modified architecture of 128 bit byte substitution module using a single 32 bit byte substitution
module to reduce area.The AES encryption and decryption algorithm were designed using Verilog HDL. The
functionality of the modules were checked using ModelSim. The simulations were carried out in ModelSim and
Quartus II. The algorithm was implemented in FPGA and achieved a 2% reduction in the total logic element
utilization
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
A Survey on Various Lightweight Cryptographic Algorithms on FPGAIOSRJECE
In today’s rapid growing technology, digital data are exchanged very frequently in seamless wireless networks. Some of the real time applications examples which are transmitted quickly are voice, video, images and text but not limited to high sensitive information like transaction of creditcard, banking and confidential security numbers/data. Thus protection of confidential data is required with high security to avoid unauthorised access to Wireless networks. This can be done by a technique called ‘Cryptograhy’ and there are two crytography techniques available (such as symmetrical & asymmetrical techniques). The focus in this paper would be on Lightweight symmetric crytography. Lightweight cryptography is used for resource-limited devices such as radio frequency identification (RFID) tags, contactless smart cards and wireless sensor network. In this paper comparative study of selected lightweight symmetric block ciphers such as AES, PRESENT, TEA and HUMMINGBIRD is presented.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
High Speed VLSI Architecture for AES-Galois/Counter ModeIJERA Editor
Galois/Counter Mode of Operation (GCM) is a block cipher mode operation used to provide encryption and
authentication using universal Hashing based on multiplication over binary Galois/Finite Field.GCM can be
implemented on both hardware and software effectively and efficiently. GCM supports pipelined and
parallelized implementations to have minimal computational latency in order to be useful at high data rates.
However need for continual performance improvement is still presented due to continuous increase in network
bandwidth and inefficiency of existing parallelization methods. This paper presents use of modified parallel
GHASH module and modified key Expansion module to improve overall efficiency. GCM architecture is
modeled in Verilog HDL and Simulated in Xilinx ISE. ASIC implementation is done on 130 nm CMOS
technology. Test case 4 of NIST submission for Galois/Counter Mode (GCM) is also verified.
The importance of cryptography knuckle down to the security in electronic data transmissions has gained an essential relevance during past years. Cryptography security mechanisms uses some algorithms to muddle the data into unreadable text with a key which can only be decoded/decrypted by one who has that associated key for the locked data. Cryptography techniques are of two types: Symmetric & Asymmetric. In this paper we’ve used symmetric cryptography method-Advance Encryption Standard algorithm with 200 bit block size as well as 200 bit key size. We’ve used 5*5 matrix to implement same 128 bit conventional AES algorithm for 200 bit block size. After implementing the algorithm, the proposed work is compared with 128,192 & 256 bits AES techniques in context with Encryption and Decryption Time & Throughput at both Encryption and Decryption ends.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Implementation and Design of AES S-Box on FPGAIJRES Journal
The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. This research investigates the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Xilinx Design Suite 14.5 software is used for simulation and optimization of the synthesizable VHDL code. All the transformations of both Encryptions is simulated using an iterative design approach in order to minimize the hardware consumption. Virtex 6 Family devices are utilized for hardware evaluation. Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. Theoretically, the design reduces the overall delay and efficiently for applications with high-speed performance. This approach is suitable for FPGA implementation in term of gate area. The hardware, total area and delay are presented.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASICpaperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
High throughput FPGA Implementation of Advanced Encryption Standard AlgorithmTELKOMNIKA JOURNAL
The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial
applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm.
Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural
properties. The AES architecture with the enhanced mix column to be proposed with reduced number of
transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES
Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS
technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding
the VLSI design environment. The simulation results of the proposed structure are performed with the
minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS
technology based AES Algorithm is integrated into the backend based chip technology.
VLSI Architecture for Nano Wire Based Advanced Encryption Standard (AES) with...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology.
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Design and Implementation A different Architectures of mixcolumn in FPGA
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
DOI : 10.5121/vlsic.2012.3402 11
Design and Implementation A different
Architectures of mixcolumn in FPGA
Sliman Arrag1
, Abdellatif Hamdoun 2
, Abderrahim Tragha 3
and Salah eddine
Khamlich 4
1
Department of Electronics and treatment of information
UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco
arragsliman@yahoo.fr
2
Department of Electronics and treatment of information
UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco
alhamdoun@yahoo.fr
3
Department of computing and Mathematics
UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco
a.tragha@univh2m.ac.ma
4
Department of Electronics and treatment of information
UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco
khamlich.salah@gmail.com
ABSTRACT
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by
using different architecture of mixcolumn. We then review this research investigates the AES algorithm in
FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera
Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of
transformations of both Encryptions and decryption are simulated using an iterative design approach in
order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware
evaluation.
KEYWORDS:
AES, Mixcolumn , FPGA, VHDL code, encryption.
1. INTRODUCTION
The cryptographic algorithms became the main proceeding for protection of very important data,
the security objective called confidentiality [1-3] being the one taken into account by their
hardware implementation and by their integration into the present-day communication systems.
A number of the encryption/decryption algorithm the cryptographie has been developed [2-4].
Keeping pace with maturity of the security technology the hackers, the electronic eavesdroppers,
electronic frauds and the virus have been coming into the field with new improved techniques for
to attack the security mechanism [17], [19]. So to protect any attack to the valuable information
source and their transmission, the algorithm Advanced Encryption Standard (AES or Rijndael), a
Federal Information Processing Standard is approved by National Institute of Standards and
Technology (NIST) [4], [7], [8], [11].But AES has 10 round of complex algebraic and matrix
operation which involve high processing power and introduce delay in encryption and decryption
process. For this reason at the beginning of this work the speed is treated as a major issue and
concentration is provided on hardware based implementation. Field Programmable Gate Array
based implementation is chosen in this operates as FPGA offers lower cost, flexibility and
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
12
reasonable performance than ASIC (Application Specific Integrated Circuit) implementation.
Beforehand researcher proposed application of AES processor on FPGA hardware place a few
security features since earlier version of the FPGA available in the market was low capacity.
Newly the development of a AES CPU using VHDL and its implementation on FPGA Xillinx
without sacrificing any security feature of the algorithm is reported [22]. It offers many FPGA
high capacities in various families. Literatures [10], [12], [13], [18], [20-21] describe design and
implementation of AES processor in the FPGA platform.
This paper presents a hardware implementation for the AES (Advanced Encryption Standard)
symmetric cryptographic algorithm, under VHDL programming language by using different
architecture of Mixcolumn and a hardware simulation of the resulted ciphering & deciphering
module.
2. THE BASIC CRYPTOGRAPHIC ARCHITECTURE
Figure 1. The basic AES-128 cryptographic architecture
AES algorithm is a FIPS standard and is a symmetric key [5], [9], in which the sender and
recipient use only key for encryption and decryption. The data block length is fixed to be 128
bits (Nb = 4 words), while the length of the cipher key can be 128, 192 or 256 bits, and be
represented by Nk = 4, 6, or 8 words respectively. Moreover, the AES algorithm is an iterative
algorithm. The iterations are called rounds, and the total number of rounds, Nr is 10, 12, or 14,
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
13
when the key length is 128, 192, or 256 bits, respectively. The 128 bit plaintext block is divided
into 16 bytes. These bytes are mapped to a 4 x 4 array called the State, and all the internal
operations of the AES algorithm are performed on the State. Each byte in the State is denoted by
Si;j , (0 < i, j < 5) and is considered as an element of Galois Fields, GF(28). The irreducible
polynomial used in the AES algorithm to construct, GF(28) field is
( ) 8 4 3
m x x x x x 1= + + + + . (1)
In (Figure 1) AES encryption processes are presented. In the encryption of the AES algorithm,
each round except for the final round consists of four transformations: the Sub__Bytes(), the
Shift__Rows(), the Mix__Columns(), and the Add__RoundKey(), while the final round does
not have the MixColumns() transformation.
The algorithm AES It can be cut in three blocks:
Initial Round: It is the first and simplest of the stages. it only counts one operation: Add Round
Key.
Remark: The inverse of this operation bloc it is herself.
N Rounds: N being the number of iterations. This number varies according to the size of the
key used. (128 bits need N=9, 192 bits need N=11 need 256 bits. N =13. This second stage is
constituted of N iterations including each the four following operations: Sub Bytes, Shift Rows,
Mix Columns, Add Round Key.
Final Round: This stage is nearly identical to one of the N iterations of the second stage. The
only difference is that it doesn't include the operation Mix Columns
2.1. ADDROUN-key
In this transformation, a round key is added to the State by a simple bit wise XOR operation (that
is a sum in Galois Fields). Each tower key consists of four words from the key schedule
procedure
Figure 2.addround-key bloc
2.2. SubBytes
This transformation is a non-linear byte substitution that operates independently on each byte
of the State using a substitution table (Sbox) [3]. We construct this S-box, which is reversible, by
composing two transformations [9]:
• 1. Taking the multiplicative inverse in the finite field GF(28) with
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
14
( ) 8 4 3
m x x x x x 1= + + + + (1)
• As irreducible polynomial; the element {00} is mapped onto itself.
2. Applying an affine (over GF (2) [1], [8]) transformation defined by:
( ) ( )
( ) ( )
' bi b i 4 mod8 b i 5 mod8
b i 6 mod8 b i 7 mod8 ci
= ⊕ + ⊕ + ⊕
+ ⊕ + ⊕
bi
(2)
• For 0 ≤ i < 8, where bi is the ith bit of the byte and ci is the ith bit of a constant byte c
with the value {63}.
Figure 3. Sub-Byte bloc
• Remark: The function inverse named Inv_SubBytes consists in applying the same function but
this time while using Inv_SBox that is the inverse table of SBox.
2.3. Shif-Rows
In this transformation, the bytes in the last three rows of the State are cyclically shifted over
different numbers of bytes (offsets). The first row, row 0, is not shifted. Row 1 of the State is left
shifted by 1 byte position; row 2 is left shifted by 2 byte positions; row 3 is left shifted by 3 byte
positions.
• Remark: The inverse function of this Inv_ShiftRoxs operation consists in replacing the shift on
the left on the right by a shift.
Figure 4. Shift-row bloc
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
15
2.4. MixColumns
This transformation [9] operates on the State column-by-column, treating each column as
a four-term polynomial over GF(28). These polynomials are multiplied modulo (x4 + 1)
with a fixed polynomial a(x), specified in the standard.
Figure 5. Mix-column bloc
Figure 6. Exemple of Multiplication the Mixcolumn
Result [1,1] = 02•D4 XOR 03•BF XOR 01•5D XOR 01•30
• Remark: The inverse function of this operation, InvMixColumns, consists in multiplying the
State_out matrix by the inverse of the constant matrix.
Figure 7. Matrice of Multiplication inverse the Mixcolumn
Previous work
There exist many presentations of hardware implementations of AES algorithms in literature. In
2001, Elbirt et al., [6] compared five candidate algorithms for AES using Field-Programmable
Gate Array (FPGA) implementations. Later FPGA implementations demonstrate better
utilization of FPGA resources. Several architectures using dedicated on-chip memories
implementing S-boxes and Mix-column were developed [23] [24] [25] [26] [27]. Recent research
focused on fast pipelined, paralleled and optimal power calculation for the cryptography AES
implementations in both FPGA [13] [28] [29] [30] [31] [32]. Unfortunately, most of those
implementations are too costly for practical applications.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
16
In this paper, we have developed compared and implemented our new different architectures of
mix-column:
1-Methods permit to calculate the products in GF (28) (architecture (1).
2- Galois Multiplication lookup tables (architecture 2).
3- Properties of the binary calculation (architecture 3).
To achieve a high throughput with small area. The rest of the paper is organized as follows:
Section 3. Implementation of AES (Ciphering & Deciphering) in FPGA.
Section 4.simulation & interpretation.
Section 5 concludes the paper.
2.4.1. methods permit to calculate the products in GF (28).
a) Mathematical application (architecture 1) [14]
{0D}* M(x) = (m0 + m5 + m6) + (m1 + m5 + m7) x + (m0 + m2 + m6) x2 + (m0 + m1 +
m3 + m5 + m6 + m7) x3 + (m1 + m2 + m4 + m5 + m7) x4+ (m2 + m3 + m5 + m6) x5 +
(m3 + m4 + m6 + m7) x6 + (m4 + m5 + m7) x7. (3)
{0E}* M(x) = (m5 + m6 + m7) + (m0 + m5) x + (m0 + m1 + m6) x2 + (m0 + m1 + m2 +
m5 + m6) x3 + (m1 + m2 + m3 + m5) x4+ (m2 + m3 + m4 + m6) x5 + (m3 + m4 + m5 +
m7) x6 + (m4 + m5 + m6) x7. (4)
{0B}* M(x)= (m0 + m5 + m7) + (m0 + m1 + m5 + m6 + m7) x + (m1 + m2 + m6 + m7)
x2 + (m0 + m2 + m3 + m5) x3 + (m1 + m3 + m4 + m5 + m6 + m7) x4+ (m2 + m4 + m5 +
m6 + m7) x5 + (m3 + m5 + m6 + m7) x6 + (m4 + m6 + m7) x7. (5)
{09}* M(x) = (m0 + m5) + (m1 + m5 + m6) x + (m2 + m6 + m7) x2 + (m0 + m3 + m5 +
m7) x3 + (m1 + m4 + m5 + m6) x4+ (m2 + m5 + m6 + m7) x5 + (m3 + m6 + m7) x6 + (m4
+ m7) x7. (6)
{03}* M(x) = (m0 + m7) + (m0 + m1 + m7) x + (m1 + m2) x2 + (m2 + m3 + m7) x3 +
(m3 + m4 + m7) x4+ (m4 + m5) x5 + (m5 + m6) x6 + (m6 + m7) x7. (7)
{02}* M(x) = (m7) + (m0 +m7) x + (m1) x2 + (m2 + m7) x3 + (m3 + m7) x4+ (m4) x5 +
(m5) x6 + (m6) x7. (8)
{01}* M(x) = M(x) (9)
b) Galois Multiplication lookup tables (architecture 2)
Commonly, rather than implementing galois multiplication, Rijndael implementations simply use
pre-calculated lookup tables to perform the byte multiplication by 02, 03, 09, 0B, 0D, and
0E.[15].
These lookup tables are as follows:
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
17
Multiplication by 02
Figure 8. Lookup table of multiplication by 02
Note: Multiplication by 03, 09, 0B, OD and 0E [15]
c) Properties of the binary calculation (architecture 3)
According to the two architectures previous we were able to achieve other method based on
the Properties of the binary calculation that have for goal the easiness the use of this operation to
the material level you find the manner and the stages that we followed in order to calculate the
multiplication mixcolumn below:
Multiplication by 01 (00000001 in binary): The number remains unaltered
Multiplication by 02 (00000010 in binary): The bits of the number are baffled toward the left:
N = 10101110 = > 2N = 101011100
Since the operations make themselves in a number finished of the values (field of Galois GF (28)
of 256 values), the MSB of 2N must be omitted:
2N = 101011100
2N = 01011100
If the MSB was (that we have just omitted) a '0', then 2N are the final result of the multiplication:
2N = 01011100
If the MSB was (that we have just omitted) a '1', what is the case in this example, then it is
necessary to add (XOR) the binary number again 00011011 (1B) to 2N in order to compensate
the loss of the MSB caused (provoked) by the shift:
2N XOR 00011011 = 01011100 XOR 00011011 = 01000111 2N = 01000111
For the Multiplications (03; 09; 0B; 0D; 0E):
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
18
we take The MSB like a mask and one calculates the operations (temp1, temp2 and temp3) of
shift on the left to add by the number (1B) in order to compensate the loss of the MSB caused
(provoked) by the shift.
and_mask := m(7) & m(7) & m(7) & m(7) & m(7) & m(7) & m(7) & m(7);
temp1:= m(6 downto 0) & '0' xor (("00011011") and and_mask);
and_mask := temp1(7) & temp1(7) & temp1(7) & temp1(7) & temp1(7) & temp1(7) & temp1(7)
& temp1(7);
temp2:= temp1(6 downto 0) & '0' xor (("00011011") and and_mask);
and_mask := temp2(7) & temp2(7) & temp2(7) & temp2(7) & temp2(7) & temp2(7) & temp2(7)
& temp2(7);
temp3:= temp2(6 downto 0) & '0' xor (("00011011") and and_mask);
Multiplication par 03 (00000011 en binaire) :temp1 xor m
Multiplication par 09 (00001001 en binaire) : temp3 xor m
Multiplication par 0B (00001011 en binaire) : temp1 xor temp3 xor m
Multiplication par 0D (00001101 en binaire) : temp2 xor temp3 xor m
Multiplication par 0E (00001110 en binaire) : temp1 xor temp2 xor temp3
Note => &: Operators of concatenation
3. Implementation of AES (Ciphering & Deciphering) in FPGA:
To concretize that our modifications give a better results in terms of area and speed than the
previous work, we compare the encryption /decryption codes (original and modified) based on
the three models of mix-column. The comparison considered two criteria: chip speed and area
utilization. The design was implemented on an Cyclone III (EP3C80F780C6 model) device.
Both designs were synthesized using Quartus II v9.1 tool. As shown in Table 1, an increase in
speed about 20% was achieved in our design and a reduction in area about 12% was achieved in
our design. On the other side, since we use Properties of the binary calculation to perform Mix-
Column transformation, we the other encryption (model 1 and 2) design needs more memory (as
shown in Table 1).
Implementation uses the VHDL programming language that nowadays is commonly a language
used very established for FPGA [16]. The drawing & the software of the simulation is Quartus II.
The encryption block is represented in Figure 9, where the main signals used by the
implementation are shown.
Figure 9. AES (ciphering & decoding) block
donner[127..0]
clef [127..0]
clk
rst
e_d
sortie[127..0]
aes_128
inst
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
19
Table1. Comparative table between different blocks constitute AES algorithm
we take in consideration the different architecture (model 1,2 and 3) of Block Mixcolumn that we
already treated, under VHDL language in the Circuit Cyclone III (EP3C80F780C6 model) which
is a low resource: 81264 logical elements; 430 pine to enter / exit; Embedded Multiplier 9-bit
elements 488; capacity of memory 2810880bits; 4PLL.The main signals are: the clock of the
system(CLK), the system reset (RST), signal of the load which load the key and given them and
signal that permits to encode and to decipher given them. A summary of the occupied resources
is presented in the comparative table. (Table 1)
• According to the comparative table we can notice that with first architecture of AES-128 (based
on the model 1 of mixcolumn) of the setting in .implementation occupies more that (75840
slices) of the device, when the second (based on the model 3 of mixcolumn) need of the setting in
.implementation roughly (75147tranches) of capacity total of the device, on the other hand the
last architecture of AES-128 has (based on the model 2 of mixcolumn) need (80829) of the
device.
The conclusion is that the last (model 3) bet in implementation is more efficient than architecture
of the first and the third, about the number of occupation of resources of the device.
4. SIMULATION & INTERPRETATION
Each round has 4 operations and it is iterative in nature. So the output of first round is fed to the
second round as input data and performs the same operations with another set of keys. This
process continued until the last round reach. In the last round, there is no mix-column operation.
The State array obtained after the last round is the required cipher text for transmission
Figure 10 and 11: shows the simulation results of the encrypt and decrypt data, we give 1bit e_d
(to control the encryption and decryption ,e_d=1 Ciphering else Deciphering ), 128 bit plaintext
(data that we need to encrypt) and 128 bit key (the key used also to generate another keys), of
course clock (clk) was used to synchronize the various blocks and rst representing the reset the
Implementation FPGA Device
Total
pins
logic cells
Peak virtual
memory
Megabyte
Total
registers
Total
memory
bits
SBOX /invSBOX 18 9 195 1 2048
Bytsub/Invbytesub 285 129 203 1 32768
Shiftrow/Invshiftrow 285 128 183 128 0
Mixcolumn_arch1 285 224 183 128 0
Mixcolumn_arch2 285 200 183 128 0
Mixcolumn_arch3 285 200 195 128 0
InvMixcolumn_arch1 285 372 185 128 0
InvMixcolumn_arch2 285 959 206 128 0
InvMixcolumn_arch3 285 360 183 128 0
Generation_de_clef 261 992 191 0 0
Aes_128_arch1 387 75840 370 128 0
Aes-128_arch2 387 80829 582 128 0
Aes_128_arch3 387 75147 368 128 0
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
20
given if equals 1, finally, we will have in 128 bit output (cyphertext).we use for our simulation
QuartusII simulator.
The diagrams retailed of the simulation the processes for the setting in implementation AES are
presented below, in Figure (10 and 11).The length total of the process of the ciphering is (124s)
and some decoding is (277s).
Ciphering :( figure10)
e_d:1
Plaintext: hamdoun_&_tragha
Key: arragsliman_miti
cyphertext:8[139][195]S[189] :[190]P[206][221][153][132][205]bI*
Figure 10. Simulation of the ciphering of AES-128
Deciphering :( figure 11)
e_d:0
plaintext :8[139][195]S[189] :[190]P[206][221][153][132][205]bI*
Key: arraglsiman_miti
Cyphertext: hamdoun_&_tragha
Figure 11. Simulation of the decoding of AES-128
During our implementation, we met several difficulties among which we mention:
- Differentiation in time of execution between the ciphering and the decoding because of the
structure of some functions and we could remedy this problem by optimization of the code
- The problems of battery overflow caused by the operating system, and we think that it is
preferable to work with machines of big performances (RAM, speed of clock, cache memory.).
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
21
- Calculate it binary in field of Galois notably the multiplication and the inverses of the matrixes.
- The description sometimes dark of the algorithm of RIJNDAEL and especially in the phase of
decoding.
This system of cryptage is used in the domains industrial, commercial and financial and on an
increasing number of the PCs. its domination on the market increases daily.
5. CONCLUSIONS
In this paper, we have presented a novel FPGA implementation of the encryption algorithm AES
under VHDL utilizing high performance Mix-column/inv-Mix-column which uses Properties of
the binary calculation.
The result shows the FPGA implementations allow us to increase flexibility, lower costs, and
reduce time to release enhanced cryptographic equipment, providing a satisfactory level of
security for communication applications, or other electronic data transfer processes where
security is needed.
The modification (AES by using architecture 3 of Mix-column) of gives an 12% reduction in
area and 20% increase in speed compared with the original design (AES by using architectures 1
and 2 of Mix-column) . Our design gives the highest throughput and area utilization over all the
Iterative Looping based FPGA implementations. The decryption algorithm is implemented and
gives better results than the design in previous work.
This compact design can help in implementing AES for smart cards, RFID Tags, and wireless
sensors. This design prevents timing attack on mix-columns as the resultant columns take the
same duration not depending on multiplicand.
Our optimized and Synthesizable VHDL code is developed for the implementation of both
encryption and decryption process. Each program is tested with some of the sample vectors
provided by NIST and output results are perfect with minimal delay. Therefore, AES can indeed
be implemented with reasonable efficiency on an FPGA, with the encryption and decryption
taking an average of 124 and 277(s) respectively (for every 128 bits). The time varies from chip
to chip and the calculated delay time can only be regarded as approximate.
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