This document summarizes key aspects of RF transceiver architecture, including: 1) Receiver linearity is characterized by IP3 and P1dB, while noise is characterized by SNR and NF. Sensitivity and dynamic range are also important. Channel filtering provides interference rejection and relaxes linearity requirements. 2) Nonlinearity in amplifiers generates harmonics and intermodulation products. IP3 characterizes the input level where an IM3 product is equal to the fundamental. 3) Thermal noise, flicker noise, and shot noise all contribute to overall receiver noise. Noise figure quantifies the degradation in SNR and cascaded stages are analyzed using Friis' formula.

1. RFIC Design
Lecture 4:
Transceiver Architecture

2. RFIC Design
4: Transceiver Architecture Slide 2
Outline
 Receiver :
– Linearity -> IP3, P1dB
– Noise -> SNR
– Sensitivity & Dynamic Range
– Channel filtering
 Transmitter

3. RFIC Design
4: Transceiver Architecture Slide 3
Nonlinearity
 For nonlinear amplifier, its TF can be represented
as :
 If
 Results in Harmonics.
 Higher order harmonics contain higher power of A

4. RFIC Design
4: Transceiver Architecture Slide 4
Odd symmetry
 Differential or Balanced Circuit
 Even order terms disappear
 Even harmonics are absent

5. RFIC Design
4: Transceiver Architecture Slide 5
1-dB compression point
 The input level that causes the small-signal gain to
drop by 1dB.
 Because of : Nonlinearity
 Around -25~-20dBm(63.2m ~ 35.6mV in 50Ω system)

6. RFIC Design
4: Transceiver Architecture Slide 6
Desensitization and Blocking
 Cause : A small signal is received and accompanied
with a strong interference.
 If a3 is negative, then gain is reduced.
 RF receiver must withstand 60~70dB signal
difference.

7. RFIC Design
4: Transceiver Architecture Slide 7
Cross Modulation
 Nonlinear effect
 Cause : A small signal is received and accompanied
with a strong interference.
 If and

8. RFIC Design
4: Transceiver Architecture Slide 8
Intermodulation(I)
 Harmonics distortion is not very useful to
characterize nonliearity.
 ∵ For examples, a low pass filter reduce the
hamonics.

9. RFIC Design
4: Transceiver Architecture Slide 9
Intermodulation(II)
 Perform “two-tone” test.
 If
 Then main part
 and harmonics

10. RFIC Design
4: Transceiver Architecture Slide 10
Intermodulation(III)
 We call the components at and the 2w1±w2 and
2w2±w1 third-order intermodulation products
 Note the 2w1- w2 and 2w2- w1 tone. It comes
closest to the main tone due to nonlinearity effect.
 Ex : A1=A2, if a1A=1V and a3A3/4=10mV
then we say IM componet is -40dBc, where c means
with respect to the carrier.

11. RFIC Design
4: Transceiver Architecture Slide 11
Intermodulation(IV)
 IM is a troublesome effect in RF system.
 IM causes a weak signal is corrupted by two strong
interference.
 While operating by AM, it still degrades the PM.
Because zero-crossing points are still affected.
 The effect can not be observed from Harmonic
distortions.

12. RFIC Design
4: Transceiver Architecture Slide 12
Intermodulation(V)
 IP3 : Third intercept point
 It is very useful to characterize the linearity
IM3 component increases with A3.
 IIP3 is the input IP3 and OIP3 is at output.
 Figures (a) in linear scale and (b) in log scale.

13. RFIC Design
4: Transceiver Architecture Slide 13
Intermodulation(VI)
 How to calculate IP3
 Let
 Suppose
 then

14. RFIC Design
4: Transceiver Architecture Slide 14
Intermodulation(VII)
 How to measure IIP3 with a single measurement
 While
 then

15. RFIC Design
4: Transceiver Architecture Slide 15
Intermodulation(VIII)
 How to calculate SNR for IM effect
 Suppose
 Then
 Ex.

16. RFIC Design
4: Transceiver Architecture Slide 16
IIP3 & P1dB
 The theoretically relationship is

17. RFIC Design
4: Transceiver Architecture Slide 17
Cascade Nonlinear Stages
 If
 then

18. RFIC Design
4: Transceiver Architecture Slide 18
Cascade Nonlinear Stages
 Practical usage :
 Approximation:
 More cascade stages

19. RFIC Design
4: Transceiver Architecture Slide 19
General Considerations
 Receiver :
– Linearity -> IP3, P1dB
– Noise -> NF
– Sensitivity & Dynamic Range
– Channel filtering

20. RFIC Design
4: Transceiver Architecture Slide 20
Thermal Noise
 The PDF is Gaussian
 The PSD is given by:
– Mean square noise voltage

21. RFIC Design
4: Transceiver Architecture Slide 21
Thermal Noise
 In the MOSFET
 Short channel: g > 2 ( process dependent )
 Long channel: g =2/3

22. RFIC Design
4: Transceiver Architecture Slide 22
Flicker noise
 Flicker noise
 It arise from random trapping of charge at the
oxide-silicon interface of MOSFETs.
 K is a constant and process dependant.

23. RFIC Design
4: Transceiver Architecture Slide 23
Shot noise
 If carriers cross a potential barrier, then the overall
current actually consists of a large number of
random current pulses.
 Usually exists in the BJT
 The random component of the current is called “shot
noise” .
 It is

24. RFIC Design
4: Transceiver Architecture Slide 24
Input Referred Noise
 The overall noise of a circuit can be represented by only two
sources placed at the input:
 Ex.
 Note: The two sources are correlated here because they
represent the same mechanism.

25. RFIC Design
4: Transceiver Architecture Slide 25
Noise Figure
 NF is a measure of how much the SNR degrades as
the signal passes through system.
 Definition :
 Usually in dB unit ( 10log10)
 NF > 1
 If no input noise, NF -> ∞. (not meaningful)

26. RFIC Design
4: Transceiver Architecture Slide 26
Noise Figure Calculation
(for measurement)

27. RFIC Design
4: Transceiver Architecture Slide 27
Noise Figure Calculation
 Ex. : In 50ohm system
What is the NF?

28. RFIC Design
4: Transceiver Architecture Slide 28
Noise Figure of Cascaded Stages
 NF calculation

29. RFIC Design
4: Transceiver Architecture Slide 29
Noise Figure of Cascaded Stages
 For a special case :

30. RFIC Design
4: Transceiver Architecture Slide 30
Noise Figure of Cascaded Stages
 For general case :
 (1)
 (2)
 (1)+(2)
 Friis equation:
Available
power gain
Available power

31. RFIC Design
4: Transceiver Architecture Slide 31
Noise Figure of Lossy circuit
 Consider a lossy circuit
 Finally, we get NF = L
 Ex. If a BP filter has 3dB loss, its NF is 3dB

32. RFIC Design
4: Transceiver Architecture Slide 32
Noise Figure of Lossy circuit
 Consider a lossy circuit in the receiver chain :
 We get
 Ex : If the BP filter has 1dB loss followed by LNA with 3dB NF,
then the total NF is 4dB.
 Hence : the first filter plays a very important role for the receiver
noise performance.

33. RFIC Design
4: Transceiver Architecture Slide 33
General Considerations
 Receiver :
– Linearity -> IP3, P1dB
– Noise -> NF
– Sensitivity & Dynamic Range
– Channel filtering

34. RFIC Design
4: Transceiver Architecture Slide 34
Sensitivity
 From NF :
 We get :
 Because the RF is 50ohm system :
 Then :
,where B is bandwidth

35. RFIC Design
4: Transceiver Architecture Slide 35
Sensitivity Calculation
 Ex.:For GSM,SNRmin ~ 12dB, B = 200kHz
 If NF of the receiver path is 9dB,
Then : Sensitivity is -174+9+53+12 = -100 dBm
 If we have a specification with sensitivity of -105dBm,
Then : NF should be : -105+174-53-12 = 4dB

36. RFIC Design
4: Transceiver Architecture Slide 36
SFDR
 The upper end of DR (actually “spurious-free”
dynamic range,(SFDR) is defined as the max.
 IM <= the noise floor:
 where Noise floor=-174 dBm+NF+10log B
 Then :

37. RFIC Design
4: Transceiver Architecture Slide 37
SFDR
 Example: GSM,SNRmin ~ 12dB, B = 200kHz, NF is
9, suppose IIP3 =-15 dBm.
 Then, SFDR=2/3(-15-(-112))-12=52.7 dB
 SFDR indicates how much interference the system
can tolerate while providing an acceptable signal
quality.

38. RFIC Design
4: Transceiver Architecture Slide 38
General Considerations
 Desensitization of LNA from PA
– PA output 1W (30dBm)
– 25dBm ANT by duplexer
– LNA is with P1db of -26dBm

39. RFIC Design
4: Transceiver Architecture Slide 39
General Considerations
 Receiver :
– SNR
– Linearity -> IP3
– Sensitivity & Dynamic Range
– Channel filtering -> Receiver Architecture

40. RFIC Design
4: Transceiver Architecture Slide 40
Channel filtering
 Receiver :
– Interference Rejection
• High Q filter
• Ex : 900MHz receiver with 60db ANT of 90kHz
=> Q:~1E7

41. RFIC Design
4: Transceiver Architecture Slide 41
Channel filtering
 Receiver :
– Bandpass filter selection
• Tradeoff : In-band Loss & Out-band Rejection
• In-band Loss => High Noise (NF) & Low SNR

42. RFIC Design
4: Transceiver Architecture Slide 42
Channel filtering
 Receiver :
– Band Selection
– Channel Selection
 Reject image
 Relax linearity requirement

43. RFIC Design
4: Transceiver Architecture Slide 43
Heterodyne Receiver
 Heterodyne : the signal band is translated to much
lower frequencies (IF) so as to relax the Q required
of the channel-select filter.
 IF : intermediate frequency.
 It filters out some strong interference to relax the
linearity requirement for the following stages.

44. RFIC Design
4: Transceiver Architecture Slide 44
Problem of image
 Both desirable and undesirable frequency band are
all mixed down to IF
 Solution : We need proper “image rejection”

45. RFIC Design
4: Transceiver Architecture Slide 45
Image rejection
 Trade-off for IF frequency selection
 High IF: good image rejection, poor channel selection
 Low IF : good channel selection, image rejection

46. RFIC Design
4: Transceiver Architecture Slide 46
Image rejection
 High side injection : if wLO > win, then image is higher
than wLO.
 Low side injection : if wLO < win, then image is lower
than wLO.
 High side injection needs high VCO frequency
operation.
 Another consideration depends on the distribution of
image band noise.

47. RFIC Design
4: Transceiver Architecture Slide 47
Half IF
 If an interference is at , the signal is
down-converted to half IF .
 If the following stage suffers from nonlinearity effect,
the second order distortion of the half IF will fall
down the wanted IF band.

48. RFIC Design
4: Transceiver Architecture Slide 48
Heterodyne Receiver
 To enhance the sensitivity and selectivity,
heterodyne receiver downconverts signal two times.

49. RFIC Design
4: Transceiver Architecture Slide 49
Homedyne Receiver
 It converts the RF signal once to the baseband.
 Called Homedyne , direct-conversion, zero-IF
architecture.
 In Fig.(a), it operates properly on with double –side band
AM signal because it overlaps + and - input spectrum.
 FM & QPSK has the different spectrum in the upper and
lower band. Hence , quadrature modulation is necessary.
 Fig.(b) operated for the quadrature modulation.

50. RFIC Design
4: Transceiver Architecture Slide 50
Homedyne Receiver
 Advantages:
– No image
– Need no image rejection filter
– Monolithic integration
– LNA need no 50ohm output matching
 Disadvantage :
– DC offset
– IQ mismatch
– Filter noise
– LO leakage

51. RFIC Design
4: Transceiver Architecture Slide 51
DC offset
 DC offset is very important issue for zero-IF.
– It corrupts the signal.
– It saturates the following stages.
 It arise from :
– Device mismatch
– self-mixing
– Signal reflection
– Tx leaks to RX

52. RFIC Design
4: Transceiver Architecture Slide 52
DC offset
 (a) Self-mixing of LO signal
 (b) Strong interferer from input

53. RFIC Design
4: Transceiver Architecture Slide 53
LO Leakage
 LO Leakage : It may arise from the mismatch of the
mixer or VCO without 50% duty cycle.

54. RFIC Design
4: Transceiver Architecture Slide 54
DC offset
 Ex. DC offset arises from LO leakage :
– The VCO has 0dBm ( ~0.63V)
– After 60dB attenuation, it remain -60dBm before
LNA
– After amplified 30dB by LNA/MIXER , it becomes
10mV.
– At the meantime , the received signal is usually
30uVrms.
– Hence, the received signal need 50~70dB gain.
– Then such gain will let dc offset saturate the
amplifier chain.

55. RFIC Design
4: Transceiver Architecture Slide 55
DC offset Cancellation
 Solution 1: High pass filter can cancel DC offset
– Issue 1: Around dc signal also loses engery.
– Issue 2: A larger capacitor fail to track fast
variation in the offset voltage.
 Solutions 2 : DC free coding
– A modulation or coding method carries little
signal around the DC
– Suitable for wideband signal
 Solution 3 : Stores the dc offset
– In the TDMA system, the dc offset value can be
stored in the C1 with a switch S1.

56. RFIC Design
4: Transceiver Architecture Slide 56
DC offset Cancellation
 Issue 3:
– Mandating large C1 due to thermal noise kT/C.
– Offset due to VCO can be detected and stored.
– However, interferer signal randomly appears.
– Hence, averaged dc offset value is necessary.
stored cancelled

57. RFIC Design
4: Transceiver Architecture Slide 57
I/Q mismatch
 A homodyne incorporates Quadrate mixing for the
frequency and phase modulation scheme.
 Scheme (b) is preferred due to not interfering the
main signal path.

58. RFIC Design
4: Transceiver Architecture Slide 58
I/Q mismatch

59. RFIC Design
4: Transceiver Architecture Slide 59
Even Order Distortion
 Even Order Distortion : If two strong interferers pass
through a nonlinear , then even order harmonics
appear in the low frequency and distort the down-
converted IF signal.

60. RFIC Design
4: Transceiver Architecture Slide 60
Even Order Distortion
 IP2 : It is used to characterize even order distortion
 Solutions : Differential circuits
– Issue 1 : The front end antenna and duplexer are
usually single ended.
• Hence : Transformer is necessary for single to
differential but its loss causes higher NF.
– Issue 2 : Differential circuits consume more
power.

61. RFIC Design
4: Transceiver Architecture Slide 61
Flicker Noise
 Flicker noise :
– Its noise power is proportional to 1/f.
– It corrupts input signal significantly around DC
frequency.
– In the homedyne receiver the down-converted
signal is only amplified LNA & Mixer (~30dB).
Hence signal is still very small and prone to
corrupted by the flicker noise.
 Solution : incorporate large device size to minimize
the magnitude of flicker noise.

62. RFIC Design
4: Transceiver Architecture Slide 62
Architecture of Image
Reject Receiver

63. RFIC Design
4: Transceiver Architecture Slide 63
90° shift circuit
 A narrow band shifted by 90 ° if its spectrum is
multiplied by G(w)=-j*sgn(w), where sgn(w) is called
signum function.
 90° shift : sinwt => -coswt
Vout1 :π /2 – tan-1RCω
Vout2 : – tan-1RCω

64. RFIC Design
4: Transceiver Architecture Slide 64
Hartley Architecture

65. RFIC Design
4: Transceiver Architecture Slide 65
Hartley Architecture
 Graphical
Analysis
 Issues:
- Gain mismatch
- Phase mismatch

66. RFIC Design
4: Transceiver Architecture Slide 66
Hartley Architecture
 To analyze the effect of the phase and gain mismatch


67. RFIC Design
4: Transceiver Architecture Slide 67

68. RFIC Design
4: Transceiver Architecture Slide 68
Hartley Architecture
 For
 For general case : Resistor variation in the CMOS
process is usually 20%
 Hence : It limits the IRR to only 20dB

69. RFIC Design
4: Transceiver Architecture Slide 69
Weaver Architecture
 Weaver Architecture performs similar the technique
of 90° shift to cancel the image signal.

70. RFIC Design
4: Transceiver Architecture Slide 70
Weaver Architecture
 Graphical analysis

71. RFIC Design
4: Transceiver Architecture Slide 71
Weaver Architecture
 The drawbacks is the secondary image problem.

72. RFIC Design
4: Transceiver Architecture Slide 72
Channel permutation
 (a) Allowing A for nonlinearity and high gain for ADC
– However, the first filter suffers from noise and
linearity issue.
 (b) Relax filter noise requirement
– However, requires linear Amp
 (c) Easy to implement filter in digital circuits
– However, require linear and low thermal and
quantization noise ADC

73. RFIC Design
4: Transceiver Architecture Slide 73
Digital IF architecture
 Digital IF : Second down-conversion is performed in
the digital circuits.
 Advantages :
– Alleviate DC offset and flicker noise issue
– No IQ phase and gain mismatch issue
 Difficulty : Need high dynamic and high bandwidth
ADC.

74. RFIC Design
4: Transceiver Architecture Slide 74
Sampling IF architecture
 Sample and hold action in the ADC also perform the
down-conversion.
 Sampling frequency could be a little lower than IF
frequency.
 Still needs high performance ADC with high speed
and high linearity.

75. RFIC Design
4: Transceiver Architecture Slide 75
Subsampling Receiver
 Sampling in the time domain causes periodically
repeated spectrum in the frequency domain.
 Signal then can be down-converted by very low
frequency sampling rate.

76. RFIC Design
4: Transceiver Architecture Slide 76
Subsampling Receiver
 Drawback : Subsampling by a factor of m multiplies
the downconverted noise power of the sampling
circuit by a factor of m.

77. RFIC Design
4: Transceiver Architecture Slide 77
Direct Conversion Transmitter
 Direct conversion : the transmitted frequency is
equal to the LO frequency.
 Matching network :
– It is to provide a maximum power transferring to
the antenna.
– It also filters out the out-of-band component that
results from the nonlinearity of PA.

78. RFIC Design
4: Transceiver Architecture Slide 78
Transmitter Architecture
 Baseband / RF interface
 Quadrature modulation :

79. RFIC Design
4: Transceiver Architecture Slide 79
Transmitter Architecture
 Baseband pulse shaping

80. RFIC Design
4: Transceiver Architecture Slide 80
Transmitter Architecture
 Baseband shaping in GMSK system

81. RFIC Design
4: Transceiver Architecture Slide 81
Direct Conversion Transmitter
 Drawback : PA generated a “noisy” signal in the
view of the VCO. It corrupting the LO by means of
“injection locking” or “injection pulling”
 Solutions : to move VCO frequency away from PA

82. RFIC Design
4: Transceiver Architecture Slide 82
Two-step transmitter
 Advantages:
– Avoid the pulling effect from PA
– Better I/Q matching due to lower frequency
operation.
 Difficulty : Second BPF must reject out-of-band
signal at (w1-w2) up to 50 ~ 60 dB.

83. RFIC Design
4: Transceiver Architecture Slide 83
RF transceiver
case studies

84. RFIC Design
4: Transceiver Architecture Slide 84
Motorola FM Rx
 Motorola FM Rx

85. RFIC Design
4: Transceiver Architecture Slide 85
Philips Pager Rx
 Philips Pager Rx

86. RFIC Design
4: Transceiver Architecture Slide 86
Philips DECT Transceiver
 Philips DECT Transceiver

87. RFIC Design
4: Transceiver Architecture Slide 87
Lucent GSM Transceiver
 Lucent GSM Transceiver

88. RFIC Design
4: Transceiver Architecture Slide 88
Philips GSM Transceiver
 Philips GSM Transceiver

89. RFIC Design
4: Transceiver Architecture Slide 89
References
 B. Razavi, “RF Microelectronics,” Upper Saddle
River: Prentice-Hall,1998.