lecture-4_me_v01.pptx

Introduction to
CMOS VLSI
Design
Lecture 4:
DC & Transient Response
Greco/Cin-UFPE
(Material taken/adapted from
Harris’ lecture notes)

CMOS VLSI Design
4: DC and Transient Response Slide 2
Outline
 DC Response
 Logic Levels and Noise Margins
 Transient Response
 Delay Estimation

CMOS VLSI Design
Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
3) If the supply voltage of a chip increases, the maximum
transistor current will
4) If the width of a transistor increases, its gate capacitance will
5) If the length of a transistor increases, its gate capacitance will
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will

CMOS VLSI Design
Activity
1) If the width of a transistor increases, the current will
2) If the length of a transistor increases, the current will
3) If the supply voltage of a chip increases, the maximum
transistor current will
4) If the width of a transistor increases, its gate capacitance will
5) If the length of a transistor increases, its gate capacitance will
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will

CMOS VLSI Design
DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
– In between, Vout depends on
transistor size and current
– By KCL, must settle such that
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
Idsn
Idsp
Vout
VDD
Vin

CMOS VLSI Design
Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

CMOS VLSI Design
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn >
Vdsn <
Vgsn >
Vdsn >
Idsn
Idsp
Vout
VDD
Vin

CMOS VLSI Design
nMOS Operation
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Idsn
Idsp
Vout
VDD
Vin

CMOS VLSI Design
nMOS Operation
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Idsn
Idsp
Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout

CMOS VLSI Design
nMOS Operation
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Idsn
Idsp
Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout

CMOS VLSI Design
pMOS Operation
Vgsp > Vgsp <
Vdsp >
Vgsp <
Vdsp <
Idsn
Idsp
Vout
VDD
Vin

CMOS VLSI Design
pMOS Operation
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Idsn
Idsp
Vout
VDD
Vin

CMOS VLSI Design
pMOS Operation
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Idsn
Idsp
Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0

CMOS VLSI Design
pMOS Operation
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Idsn
Idsp
Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0

CMOS VLSI Design
I-V Characteristics
 Make pMOS is wider than nMOS such that bn = bp
Vgsn5
Vgsn4
Vgsn3
Vgsn2
Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0

CMOS VLSI Design
Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD

CMOS VLSI Design
Load Line Analysis
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Idsn
Idsp
Vout
VDD
Vin

CMOS VLSI Design
Load Line Analysis
Vin0
Vin0
Idsn
, |Idsp
|
Vout
VDD
 Vin = 0

CMOS VLSI Design
Load Line Analysis
Vin1
Vin1
Idsn
, |Idsp
|
Vout
VDD
 Vin = 0.2VDD

CMOS VLSI Design
Load Line Analysis
Vin2
Vin2
Idsn
, |Idsp
|
Vout
VDD
 Vin = 0.4VDD

CMOS VLSI Design
Load Line Analysis
Vin3
Vin3
Idsn
, |Idsp
|
Vout
VDD
 Vin = 0.6VDD

CMOS VLSI Design
Load Line Analysis
Vin4
Vin4
Idsn
, |Idsp
|
Vout
VDD
 Vin = 0.8VDD

CMOS VLSI Design
Load Line Analysis
Vin5
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD
 Vin = VDD

CMOS VLSI Design
Load Line Summary
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Idsn
, |Idsp
|
Vout
VDD

CMOS VLSI Design
DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Vin1
Vin2
Vin3
Vin4
Vout
VDD
C
Vout
0
Vin
VDD
VDD
A B
D
E
Vtn
VDD
/2 VDD
+Vtp

CMOS VLSI Design
Operating Regions
 Revisit transistor operating regions
C
Vout
0
Vin
VDD
VDD
A B
D
E
Vtn
VDD
/2 VDD
+Vtp
Region nMOS pMOS
A
B
C
D
E

CMOS VLSI Design
Operating Regions
 Revisit transistor operating regions
C
Vout
0
Vin
VDD
VDD
A B
D
E
Vtn
VDD
/2 VDD
+Vtp
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff

CMOS VLSI Design
Beta Ratio
 If bp / bn  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
Vout
0
Vin
VDD
VDD
0.5
1
2
10
p
n
b
b

0.1
p
n
b
b


CMOS VLSI Design
Noise Margins
 How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NML
NMH
Input Characteristics
Output Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range

CMOS VLSI Design
 By definition, VIH and VIL are the operational points of
the inverter where
VDD
Vin
Vout
VOH
VDD
VOL
VIL
VIH
Vtn
Unity Gain Points
Slope = -1
VDD
-
|Vtp
|
bp
/bn
> 1
Vin
Vout
0
A high gain (g) is
desirable

CMOS VLSI Design
Logic Levels
 To maximize noise margins, select logic levels at
VDD
Vin
Vout
VDD
bp
/bn
> 1
Vin
Vout
0

CMOS VLSI Design
Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
VDD
Vin
Vout
VOH
VDD
VOL
VIL
VIH
Vtn
Unity Gain Points
Slope = -1
VDD
-
|Vtp
|
bp
/bn
> 1
Vin
Vout
0

CMOS VLSI Design
Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

CMOS VLSI Design
Inverter Step Response
 Ex: find step response of inverter driving load cap
0
( )
(
)
)
(
o
i
ut
n
out
V t t
t
V
t
V
d
d
t

 

Vin(t)
Vout
(t)
Cload
Idsn(t)

CMOS VLSI Design
0
0
( )
( )
( )
( )
ou
DD
in
t
out
u t t V
d
d
t
t t
V t
V
V
t





Vin(t)
Vout
(t)
Cload
Idsn(t)

CMOS VLSI Design
0
0
(
( )
)
(
(
)
)
DD
D
o
i
D
o t
n
ut
u
V t
u t t V
V
d
d
t
t
V
V
t
t
 



Vin(t)
Vout
(t)
Cload
Idsn(t)

CMOS VLSI Design
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 

 

0
( ) DD t
out
ou
ds
t DD t
n
I t V V
V
V V
V
t t



  

  

Vin(t)
Vout
(t)
Cload
Idsn(t)

CMOS VLSI Design
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 

 

 
0
2
2
0
2
)
)
(
( )
( DD DD t
DD
out
out
out out D t
n
t
ds
D
I V
t t
V V V V
V V V V
V
t
V t
V t
b
b




   


 
   
  
 

Vin(t)
Vout
(t)
Cload
Idsn(t)

CMOS VLSI Design
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 

 

 
0
2
2
0
2
)
)
(
( )
( DD DD t
DD
out
out
out out D t
n
t
ds
D
I V
t t
V V V V
V V V V
V
t
V t
V t
b
b




   


 
   
  
 

Vout(t)
Vin(t)
t0
t
Vin(t)
Vout
(t)
Cload
Idsn(t)
nMOS – “1” transfer is bad

CMOS VLSI Design
Delay Definitions
 tpdr: rising propagation delay
– From input to rising output crossing VDD/2 (upper bound)
 tpdf: falling propagation delay
– From input to falling output crossing VDD/2 (upper bound)
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– time required for a node to charge from the 10% point to
90% ( 0.1 VDD to 0.9 VDD )
 tf: fall time
– time required for a node to discharge from 90% to 10%
point (0.9 VDD to 0.1 VDD )

CMOS VLSI Design
Tpdr = TpHL Tcdf = TpHL
tr tf
Delay Definitions

CMOS Inverter Switching
Characteristics
 Define:
– Falling delay tdf = delay time with output falling
– Rising delay tdr = delay time with output rising

43
Trajectory of a n-transistor
operating point
a. Transistor is Cut off
b. Capacitance CL is loaded with VDD
a. Applying a Vgs=VDD
b. Vout -> 0,9 to (VDD-Tth)
a. VDD-Tth -> to 0.1V

Fall-time equivalent circuit
Rise-time equivalent circuit
The fall-time is faster than the rise
time,
tf=tr/2
primarily due to different carrier
mobilities associated with the p and
n- devices:
µn = 2 µp
It is true considering equally
sized n and p transistors
βn = 2 βp

CMOS VLSI Design
 If the designer wants to have both n an p transistor
with the same rise and fall time:
βn / βp = 1
 This implies that channel width for the p-device must
be increased to approximately two to three times of
the n-device:
wp = 2 – 3 wn
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.90
)
polysilicon
gate
Trajectory of a n-transistor
operating point

CMOS VLSI Design
Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches

CMOS VLSI Design
RC Delay Models
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
k
g
s
d
g
s
d
kC
kC
kC
R/k
k
g
s
d
g
s
d
kC
kC
kC
2R/k
Capacitance
proportional to width
Resistance
inversely
proportional to
width
nMOS pMOS

CMOS VLSI Design
 Resistance of a uniform slab:
– R =  (l/A) = (/t) (L/W) where  is the
resistivity in ohm-cm, t is the
thickness in cm, L is the length, W is
the width, and A is the cross-sectional
area
– Using the concept of sheet resistance,
R = Rs (L/W) where Rs is called the
sheet resistance and given in ohms
per square
• Rs =  / t
 Gate Capacitance
- Cg = oxWL/tox = oxA/tox
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.90
)
polysilicon
gate
RC Delay Models

CMOS VLSI Design
MOS device capacitances
 MOS Device capacitances
– Cgs, Cgd = gate-to-channel capacitances, which are lumped at the
source and the drain regions.
– Csb, Cdb = source and drain-duiffusion capacitances to bulk (or
substrate)
– Cgb = gate –to-bulk capacitance

CMOS VLSI Design
1. Off region, where Vgs < Vt. There is no channel Cgs, Cgd = 0.
2. Non-saturated region, where Vgs - Vt. > Vds. Cgb = 0
3. Saturated region, where Vgs <-Vt. < Vds. Channel is heavely inverted.
The drain is pinched off causing Cgd = 0.
MOS device capacitances

CMOS VLSI Design
RC Delay Models
pMOS capacitance
= 2x nMOS
capacitance

CMOS VLSI Design
Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths
chosen to achieve effective rise and fall resistances
equal to a unit inverter (R).

CMOS VLSI Design

CMOS VLSI Design
3
3
2
2
2
3

CMOS VLSI Design
3-input NAND Caps
 Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3

CMOS VLSI Design
3-input NAND Caps
2 2 2
3
3
3
3C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
Resultant capacitance
per gate = 2C+3C = 5C
Parallel capacitances
3x2C+3C = 9C

CMOS VLSI Design
3-input NAND Caps
9C
3C
3C
3
3
3
2
2
2
5C
5C
5C

CMOS VLSI Design
Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
R1
R2
R3
RN
C1
C2
C3
CN
   
nodes
1 1 1 2 2 1 2
... ...
pd i to source i
i
N N
t R C
R C R R C R R R C
 

       


CMOS VLSI Design
 Estimate worst-case rising and falling delay of 2-
input NAND driving h identical gates.
h copies
2
2
2
2
B
A
x
Y

CMOS VLSI Design
h copies

CMOS VLSI Design
h copies
Parallel capacitances
2C+2C+2C= 6C

CMOS VLSI Design
4: DC and Transient Response
 Estimate rising and falling propagation delays of a 2-
h copies
6C
2C
2
2
2
2
4hC
B
A
x
Y

CMOS VLSI Design
h copies
6C
2C
2
2
2
2
4hC
B
A
x
Y
R
(6+4h)C
Y
pdr
t 

CMOS VLSI Design
h copies
6C
2C
2
2
2
2
4hC
B
A
x
Y
R
(6+4h)C
Y  
6 4
pdr
t h RC
 
Rising time: nMOS - “off”
pMOS - “on”

CMOS VLSI Design
h copies
6C
2C
2
2
2
2
4hC
B
A
x
Y

CMOS VLSI Design
h copies
6C
2C
2
2
2
2
4hC
B
A
x
Y
pdf
t 
(6+4h)C
2C
R/2
R/2
x Y
Consider that the nMOS resistance = (pMOS resistance)/2 = R/2

CMOS VLSI Design
h copies
6C
2C
2
2
2
2
4hC
B
A
x
Y
      
 
2 2 2
2 6 4
7 4
R R R
pdf
t C h C
h RC
   
 
 
 
(6+4h)C
2C
R/2
R/2
x Y

CMOS VLSI Design
Delay Components
 Delay has two parts
– Parasitic delay
• 6 or 7 RC
• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance

CMOS VLSI Design
Contamination Delay
 Best-case (contamination) delay can be substantially
less than propagation delay.
 Ex: If both inputs fall simultaneously
6C
2C
2
2
2
2
4hC
B
A
x
Y
R
(6+4h)C
Y
R
 
3 2
cdr
t h RC
 

CMOS VLSI Design
7C
3C
3C
3
3
3
2
2
2
3C
2C
2C
3C
3C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
Shared
Contacted
Diffusion
Diffusion Capacitance
 we assumed contacted diffusion on every source/drain
 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
Capacitance = 2C+2C+3C = 7C

CMOS VLSI Design
Layout Comparison
 Which layout is better?
A
VDD
GND
B
Y
A
VDD
GND
B
Y

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