The document discusses CMOS transistor theory, including: 1) It describes the MOS capacitor structure and its operating modes of accumulation, depletion, and inversion. 2) It analyzes the I-V characteristics of nMOS and pMOS transistors in the cutoff, linear, and saturation regions based on the channel charge and carrier velocity. 3) It explains the gate, source, and drain capacitances of MOS transistors and how they impact speed. The gate capacitance contributes to channel charge while other capacitances are parasitic.

1. Lecture 3:
CMOS
Transistor
Theory

2. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 2
Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance

3. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 3
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed

4. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 4
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
Vg < 0
MOS Capacitor
 Gate and body form MOS
capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
(b)
+
-
0 < Vg < Vt
depletion region
(c)
+
-
Vg > Vt
depletion region
inversion region

5. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 5
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-

6. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 6
nMOS Cutoff
 No channel
 Ids ≈ 0
+
-
Vgs
= 0
n+ n+
+
-
Vgd
p-type body
b
g
s d

7. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 7
nMOS Linear
 Channel forms
 Current flows from d to s
– e- from s to d
 Ids increases with Vds
 Similar to linear resistor
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s d
Ids

8. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 8
nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids

9. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 9
I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

10. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 10
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9)
polysilicon
gate
Cox = eox / tox

11. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 11
Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = mE m called mobility
 Time for carrier to cross channel:
– t = L / v

12. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 12
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V
m


 
  
 
 
 
  
 
 
ox
=
W
C
L
 m

13. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 13
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
 
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V


 
  
 
 
 

14. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 14
nMOS I-V Summary
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 


 Shockley 1st order transistor models

15. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 15
Example
 We will be using a 0.6 mm process for your project
– From AMI Semiconductor
– tox = 100 Å
– m = 350 cm2/V*s
– Vt = 0.7 V
 Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 l
 
14
2
8
3.9 8.85 10
350 120 μA/V
100 10
ox
W W W
C
L L L
 m


 
   
  
  
  
 
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
Vds
I
ds
(mA)
Vgs
= 5
Vgs
= 4
Vgs
= 3
Vgs
= 2
Vgs
= 1

16. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 16
pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V•s in AMI 0.6 mm process
 Thus pMOS must be wider to
provide same current
– In this class, assume
mn / mp = 2
-5 -4 -3 -2 -1 0
-0.8
-0.6
-0.4
-0.2
0
I
ds
(mA)
Vgs
= -5
Vgs
= -4
Vgs
= -3
Vgs
= -2
Vgs
= -1
Vds

17. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 17
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

18. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 18
Gate Capacitance
 Approximate channel as connected to source
 Cgs = eoxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9e0
)
polysilicon
gate

19. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 19
Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

20. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
C-V characteristics
3: CMOS Transistor Theory 20
The total value of this capacitance is called the
gate capacitance Cg and can be decomposed into
two elements, each with a different behavior.
• Obviously, one part of Cg contributes to the
channel charge.
• Another part is solely due to the topological
structure of the transistor. This component is the
subject of the remainder of this section.

21. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
Dynamic Behavior of MOS Transistor
D
S
G
B
CGD
CGS
CSB CDB
CGB

22. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
Overlap capacitance
tox
n+ n+
Cross section
L
Gate oxide
xd xd
Ld
Polysilicon gate
Top view
Gate-bulk
overlap
Source
n+
Drain
n+
W

23. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
Channel Capacitance
S D
G
CGC
S D
G
CGC
S D
G
CGC
Cut-off Resistive Saturation
Most important regions in digital design: saturation and cut-off

24. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
Channel Capacitance
WLCox
WLCox
2
2WLCox
3
CGC
CGCS
VDS /(VGS-VT)
CGCD
0 1
CGC
CGCS = CGCD
CGC B
WLCox
WLCox
2
VGS
Capacitance as a function of VGS
(with VDS = 0)
Capacitance as a function of the
degree of saturation

25. CMOS VLSI Design
CMOS VLSI Design 4th Ed.
Diffusion (Junction) Capacitance
Bottom
Side wall
Side wall
Channel
Source
ND
Channel-stop implant
N
A1
SubstrateNA
W
xj
L S