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1. CMOS VLSI Design 4th Ed.
VLSI System
Design(BECE303L)
Dr. Satheesh Kumar S
Cabin: TT(A)-102-G
Mobile: 8124424714

2. CMOS VLSI Design 4th Ed.
VLSI Design Overview
and MOSFET Theory
2

3. CMOS VLSI Design 4th Ed.

4. CMOS VLSI Design 4th Ed.

5. CMOS VLSI Design 4th Ed.
Electrical Numerical Integrator And Calculator (ENIAC).

6. CMOS VLSI Design 4th Ed.

7. CMOS VLSI Design 4th Ed.
What is VLSI ?
Very Large Scale Integration
Integration: Integrated Circuits (Within IC).
 Multiple Devices in a substrate
 How Large is Very Large?
 SSI (Small Scale Integration)
 10 to 100 transistors (7400 series)
 MSI (Medium Scale)
 100 to 1000 transistors (74000 series)
 LSI (Large Scale)
 1000 to 10000 transistors
 VLSI (Very Large Scale)
 > 10000 transistors
 ULSI (Ultra Large Scale)
 (Not so popular)

8. CMOS VLSI Design 4th Ed.
VLSI Design Flow

9. CMOS VLSI Design 4th Ed.
2: MIPS Processor Example 9
Structured Design
 Hierarchy: Divide and Conquer
– Recursively system into modules
 Regularity
– Decomposition of a large system in simple and
similar blocks as much as possible.
– Reuse modules wherever possible
– Ex: Standard cell library

10. CMOS VLSI Design 4th Ed.
 Modularity: well-formed interfaces
– Modularity in design means that the various
functional blocks which make up the larger
system must have well-defined functions and
interfaces.
– Modularity allows that each block or module can
be designed relatively independently from each
other.
– All of the blocks can be combined with ease at
the end of the design process, to form the large
system.
10

11. CMOS VLSI Design 4th Ed.
– The concept of modularity enables the
parallelisation of the design process.
– Allows modules to be treated as black boxes
 Locality
– The concept of locality also ensures that
connections are mostly between neighboring
modules, avoiding long-distance connections as
much as possible.
– Physical and temporal
11

12. CMOS VLSI Design 4th Ed. 12
nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
– Even though gate is
no longer made of metal
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
Body

13. CMOS VLSI Design 4th Ed. 13
nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S

14. CMOS VLSI Design 4th Ed. 14
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
Vg < 0
MOS Capacitor
 Gate and body form MOS
capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
(b)
+
-
0 < Vg < Vt
depletion region
(c)
+
-
Vg > Vt
depletion region
inversion region

15. CMOS VLSI Design 4th Ed. 15
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-

16. CMOS VLSI Design 4th Ed. 16
nMOS Cutoff
 No channel
 Ids ≈ 0
+
-
Vgs
= 0
n+ n+
+
-
Vgd
p-type body
b
g
s d

17. CMOS VLSI Design 4th Ed. 17
nMOS Linear
 Channel forms
 Current flows from d to s
– e- from s to d
 Ids increases with Vds
 Similar to linear resistor
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s d
Ids

18. CMOS VLSI Design 4th Ed. 18
nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids

19. CMOS VLSI Design 4th Ed. 19
Ideal I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

20. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 20
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9)
polysilicon
gate
Cox = eox / tox

21. CMOS VLSI Design 4th Ed.
 Vgc- vt = amount of voltage attracting charge to the
channel beyond the minimum required to invert from
P to n.
21

22. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 22
Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = mE m called mobility
 Time for carrier to cross channel:
– t = L / v

23. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 23
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V
m


 
  
 
 
 
  
 
 
ox
=
W
C
L
 m

24. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 24
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
 
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V


 
  
 
 
 

25. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 25
nMOS I-V Summary
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 


 Shockley 1st order transistor models

26. CMOS VLSI Design 4th Ed. 26
pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
SiO2
n
Gate
Source Drain
bulk Si
Polysilicon
p+ p+

27. CMOS VLSI Design 4th Ed. 27
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF

28. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 28
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

29. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 29
Gate Capacitance
 Approximate channel as connected to source
 Cgs = eoxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9e0
)
polysilicon
gate

30. CMOS VLSI Design 4th Ed.
C-V characteristics
3: CMOS Transistor Theory 30
The total value of this capacitance is called the
gate capacitance Cg and can be decomposed into
two elements, each with a different behavior.
• Obviously, one part of Cg contributes to the
channel charge.
• Another part is solely due to the topological
structure of the transistor.

31. CMOS VLSI Design 4th Ed.
Dynamic Behavior of MOS Transistor
D
S
G
B
CGD
CGS
CSB CDB
CGB

32. CMOS VLSI Design 4th Ed.
Overlap capacitance
tox
n+ n+
Cross section
L
Gate oxide
xd xd
Ld
Polysilicon gate
Top view
Gate-bulk
overlap
Source
n+
Drain
n+
W

33. CMOS VLSI Design 4th Ed.
Channel Capacitance
S D
G
CGC
S D
G
CGC
S D
G
CGC
Cut-off Resistive Saturation
Most important regions in digital design: saturation and cut-off

34. CMOS VLSI Design 4th Ed.
Channel Capacitance
WLCox
WLCox
2
2WLCox
3
CGC
CGCS
VDS /(VGS-VT)
CGCD
0 1
CGC
CGCS = CGCD
CGC B
WLCox
WLCox
2
VGS
Capacitance as a function of VGS
(with VDS = 0)
Capacitance as a function of the
degree of saturation

35. CMOS VLSI Design 4th Ed.
Diffusion (Junction) Capacitance
Bottom
Side wall
Side wall
Channel
Source
ND
Channel-stop implant
N
A1
SubstrateNA
W
xj
L S

36. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 36
Figure 0.3 shows NMOS and PMOS devices with drains, source, and gate
ports annotated. Determine the mode of operation (saturation, linear, or
cutoff) and drain current ID for each of the biasing configurations given
below. Use the following
transistor data: NMOS: k'n = 115μA/V2, VT0 = 0.43 V, λ = 0.06 V–1, PMOS:
k'p = 30 μA/V2, VT0 = –0.4 V, λ = -0.1 V–1. Assume (W/L) = 1.
a. NMOS: VGS = 2.5 V, VDS = 2.5 V. PMOS: VGS = –0.5 V, VDS = –1.25 V.
b. NMOS: VGS = 3.3 V, VDS = 2.2 V. PMOS: VGS = –2.5 V, VDS = –1.8 V.

37. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 37
Consider an NMOS transistor with the following parameters:
tox = 6 nm, L = 0.24 μm, W = 0.36 μm, LD = LS = 0.625 μm, CO
= 3 x 10–10 F/m, Cj0 = 2 x10–3 F/m2, Cjsw0 = 2.75x10–10
F/m. Determine the zero-bias value of all relevant
capacitances.

38. CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 38
Solution:

39. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 39
Non-ideal Transistor Theory
 Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage

40. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 40
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
 Shorter Leff gives more current
– Ids increases with Vds
– Even in saturation
n
+
p
Gate
Source Drain
bulk Si
n
+
VDD
GND VDD
GND
L
Leff
Depletion Region
Width: Ld

41. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 41
Chan Length Mod I-V
 l = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
   
2
1
2
ds gs t ds
I V V V

l
  

42. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 42
Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
1200
Vds
Ids (mA)
Vgs = 1.0
Vgs = 1.0
Vgs = 0.8
Vgs = 0.6
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Channel length modulation:
Saturation current increases
with Vds
Ion = 747 mA @
Vgs = Vds = VDD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

43. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 43
Electric Fields Effects
 Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel  Evert
 Lateral electric field: Elat = Vds / L
– Accelerates carriers from drain to source
– Long channel: v = mElat

44. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 44
Velocity Saturation
 At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Better model

45. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 45
Threshold Voltage Effects
 Vt is Vgs for which the channel starts to invert
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect

46. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 46
Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
 fs = surface potential at threshold
– Depends on doping level NA
– And intrinsic carrier concentration ni
 g = body effect coefficient
 
0
t t s sb s
V V V
g f f
   
2 ln A
s T
i
N
v
n
f 
si
ox
si
ox ox
2q
2q A
A
N
t
N
C
e
g e
e
 

47. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 47
DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
– Drain voltage also affect Vt
 High drain voltage causes current to increase.
ttdsVVV
t t ds
V V V

  

48. CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 48
Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature
Vgs
ds
I
increasing
temperature