VLSI- Unit I

VLSI Design
Techniques
UNIT I
MOS Transistor Theory and
Process Technology

VLSI Design Techniques Slide 2
Outline
 Introduction
 nMOS Transistor
 pMOS Transistor
 Threshold Voltage
 Body Effect
 Design Equations
 Second order effects
 MOS Models
 Small Signal AC characteristics
 Basic CMOS Technologies

Introduction

MOS Transistor
 Gate and body form MOS capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
Vg
< 0
(b)
+
-
0 < Vg
< Vt
depletion region
(c)
+
-
Vg
> Vt
depletion region
inversion region

Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0.
 Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-

nMOS Enhancement mode
Transistor

nMOS Cutoff
 Vgs << Vt : Transistor OFF
– Majority carrier in channel (holes)
– No current from source to drain
+
-
Vgs
= 0
n+ n+
+
-
Vgd
p-type body
b
g
s d

nMOS Linear
 Vgs > Vt , VDS <VGS -VT : Linear (Active) mode
Combined electric fields
shift channel and depletion region
Current flow dependent on VGS, VDS
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s d
Ids

nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids

pMOS Transistor

 Opposite of N-Transistor
– Vgs >> Vt : Transistor OFF
• Majority carrier in channel (electrons)
• No current from source to drain
– 0 > Vgs > Vt : Depletion region
• Electric field repels majority carriers (electrons)
• Depletion region forms - no carriers in channel
• No current flows (except for leakage current)
 Vgs < Vt , VDS=0: Transistor ON
• Electric field attracts minority carriers (holes)
• Inversion region forms in channel
• Depletion layer insulates channel from substrate
• Current can now flow from source to drain!
pMOS Transistor Operation

 Vgs <Vt , VDS >VGS -VT : Linear (Active) mode
– Combined electric fields shift channel and
depletion region
– Current flow dependent on VGS, VDS
 Vgs < Vt , VDS <VGS -VT : Saturation mode
– Channel “pinched off”
– Current still flows due to hole drift
– Current flow dependent on VGS
pMOS Transistor Operation Cont..

Threshold Voltage Concept
VGS
+
S D
p substrate
B
G
n+
n+ n+
n+
p substrate
depletion
region
n channel
The value of VGS where strong inversion occurs is called
the threshold voltage, VT

Threshold Voltage Components I
 Work function difference between the gate and the
channel, GC
• GC = F(substrate) - M for metal gate
• GC = F(substrate) - F(gate) for polysilicon gate
 Gate voltage component to change (invert) the
surface potential, 2F
• Fermi Potential, F = T ln(NA / ni)
• F ~ -0.3 V for p-type silicon substrate

Threshold Voltage Components II
 Gate voltage component to offset the depletion region
charge, QB / Cox
• Gate Oxide Capacitance per unit area, Cox = ox / tox
• Depletion region charge,

QB  2qNAsi  2F VSB
 Voltage component to offset fixed charges in the gate
oxide and in the silicon-oxide surface, QS / Cox
 Threshold adjustment by applying the ion implant-ation
into the channel, QI / Cox

The Threshold Voltage

VT  GC  2F 
QB
Cox

QS
Cox

QI
Cox

VT VT 0    2F VSB  2F
 
VT 0  VT
VSB 0
 
2q  NAsi
Cox
Body-effect
coefficient

17
Body Effect
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
 s = surface potential at threshold
- Depends on doping level NA
– And intrinsic carrier concentration ni
 = body effect coefficient
si
ox
si
ox ox
2q
2q A
A
N
t
N
C

 

 

The Body Effect
-2.5 -2 -1.5 -1 -0.5 0
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
BS
(V)
V
T
(V)

MOS Device Design Equations
I-V Characteristics

nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V



 
  
 
 
 
  
 
 
ox
=
W
C
L
 

nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
 
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V


 
  
 
 
 

nMOS I-V Summary
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 


 Shockley 1st order transistor models

Current-Voltage
Relations
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
VDS
(V)
I
D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT

Example
 We will be using a 0.6 m process for your project
– From AMI Semiconductor
– tox = 100 Å
–  = 350 cm2/V*s
– Vt = 0.7 V
 Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 l
 
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L
  


 
   
  
 
 
  
 
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
Vds
I
ds
(mA)
Vgs
= 5
Vgs
= 4
Vgs
= 3
Vgs
= 2
Vgs
= 1

pMOS I-V
 All dopings and voltages are inverted for pMOS
 Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2/V*s in AMI 0.6 m process
 Thus pMOS must be wider to provide same current

26
Ideal Transistor I-V
 Shockley long-channel transistor models
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 



27
Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
1200
Vds
Ids (A)
Vgs = 1.0
Vgs = 1.0
Vgs = 0.8
Vgs = 0.6
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Channel length modulation:
Saturation current increases
with Vds
Ion = 747 mA @
Vgs = Vds = VDD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

28
ON and OFF Current
 Ion = Ids @ Vgs = Vds = VDD
– Saturation
 Ioff = Ids @ Vgs = 0, Vds = VDD
– Cutoff
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
Vds
Ids (A)
Vgs = 1.0
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Ion = 747 mA @
Vgs = Vds = VDD

Second Order Effects in MOSFET
 Second order effects
– Threshold Voltage
– Body Effect
– Sub-Threshold Voltage
– Chennel-Length Modulation
– Mobility Variation
– Fowler-Nordheim Tunneling
– Drain Punch through
– Impact Ionization-Hot electrons

Drain-induced barrier lowering
or DIBL (for low L)
VT
LowVDS threshold
VDS
Threshold Variations
L
Long-channel
threshold
Threshold as a function of the
length (for low VDS)
VT
Short-channel
threshold

31
Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
 s = surface potential at threshold
– Depends on doping level NA
– And intrinsic carrier concentration ni
  = body effect coefficient
 
0
t t s sb s
V V V
  
   
2 ln A
s T
i
N
v
n
 
si
ox
si
ox ox
2q
2q A
A
N
t
N
C

 

 

32
Body Effect Cont.
 For small source-to-body voltage, treat as linear

33
Sub Threshold Voltage
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
– Adversely effect circuits such as dynamic charge
storage nodes.
 Gate leakage
– Tunneling through ultra thin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current

34
Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
 n is process dependent
– typically 1.3-1.7
 Rewrite relative to Ioff on log scale
 S ≈ 100 mV/decade @ room temperature
0
0e 1 e
gs t ds sb ds
T T
V V V k V V
nv v
ds ds
I I


   
 
 
 
 
 

35
Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD
– A and B are tech constants
– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (tox > 20 Å)
 Critically important at 65 nm and below (tox ≈ 10.5 Å)
From [Song01]

36
Junction Leakage
 Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)
n well
n+
n+ n+
p+
p+
p+
p substrate

37
Diode Leakage
 Reverse-biased p-n junctions have some leakage
 At any significant negative diode voltage, ID = -Is
 Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/m2 (negligible)
e 1
D
T
V
v
D S
I I
 
 
 
 
 

38
Gate-Induced Drain Leakage
 Occurs at overlap between gate and drain
– Most pronounced when drain is at VDD, gate is at
a negative voltage
– Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

39
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
• Where
 Shorter Leff gives more current
– Ids increases with Vds
– Even in saturation
n
+
p
Gate
Source Drain
bulk Si
n
+
VDD
GND VDD
GND
L
Leff
Depletion Region
Width: Ld
2
( ( ))
si
d ds gs t
A
L V V V
qN

  
2
( ) (1 )
2
ds gs t ds
K W
I V V V
L
l
  

40
Chan Length Mod I-V
 l = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
   
2
1
2
ds gs t ds
I V V V

l
  

Gate voltage and the channel
Vds < Vgs - Vt
gate
drain
source
current
Id
gate
drain
source
current
Id
gate
drain
source
Id
Vds = Vgs - Vt
Vds > Vgs - Vt

42
Mobility Variation
 High Evert effectively reduces mobility
– Collisions with oxide interface
. . . ( )
. ( )
averagecarrier drift velocity v
Electric Field E
 

Fowler-Nordheim Tunneling
 When gate oxide is very thin a current ca flow from
the gate to source or drain by electron tunneling
through the gate oxide.
 Current is proportional to the area of the gate of the
transistor.
 Where Eox is the electric field across the gate oxide
and Eo and C1 are constants.
2
1
o
ox
E
E
FN ox
I CWLE e



44
Drain Punch through
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
– Drain voltage also affect Vt
 High drain voltage causes current to increase.
ttdsVVV
t t ds
V V V

  

Hot Carriers
 Electrons become “hot”, i.e. reaching a critical high
level of energy, under intense electric field which
occurs when the channel is short.
 Ecrit ≈ 104 V/m
 Hot electrons can leave the silicon and tunnel into
the gate oxide.
 Electrons trap in the gate oxide increase NMOS
threshold and decrease PMOS threshold.
 Hot electronics impact the drain dislodging holes
that are then swept toward the negatively charged
substrate and appear as a substrate current and this
effect is known as “Impact Ionization”.

MOS modeling
 Modeling can be defined as “The method of finding the
parameter values for fixed simulator model equations”
 MOS modeling -Writing a set of equations that link voltages and
currents
 Behavior of the device can be simulated and predicted
 Basic MOS model components
1. Equations describing Ids (Vds) and Ids (Vgs)
2. Parameters that link the technology being used for
fabrication

Requirements of good MOS model
 Good I-V characteristic accuracy
 Meet charge conservation requirement
 Correct values of small-signal quantities
 Good prediction for white and 1/f noise
 Ability to provide results even when device operation
is quasi static
 Ability to include all physical mechanisms for sub-
micron devices

MOSFET parameters
 The table 1 shows the most frequently used MOS parameters

MOSFET ac response
MOSFET ac response is routinely expressed in terms of small-
signal equivalent circuits. This circuit can be derived from the
two-port network shown below:
MOSFET
input output
G
S
D
S
The input looks like an open circuit, except for the presence
of the gate capacitor.
At output, we have a current ID which is controlled by VG and VDS.
ID = f (VG, VDS )

MOSFET small-signal equivalent
circuit
DS
DS
D
G
G
D
D
G
DS
V
V
I
V
V
I
I
V
V









d
d
g
m
d v
g
v
g
i 

DS
G
D
m
V
V
I
g



G
DS
D
d
V
V
I
g



gm = trans-conductance, gd = drain or channel conductance
Any ac signal in VG or VDS will result in corresponding ac
variation in ID
where and
Note: id, vg and vd are small-signal ac currents and voltages.
They are different from ID, VG and VDS which are dc currents
and voltages.

Small-signal equivalent circuit
So, the equivalent circuit at low-frequency looks like
(neglecting the gate capacitance low frequency):
For high-frequency, we have to include the capacitive effects:

MOSFET small-signal parameters
When VDS < VDS,sat (i.e., below pinch-off or linear region)
d G T DS
( )
g V V V

  
m(linear) DS
g V


When VDS > VDS,sat (i.e., above pinch-off or saturation region)
gd = 0
m(sat) T
( )
G
g V V

 
Note: the parameters depend on the dc bias, VG and VDS

Frequency response of MOSFET
The cut-off frequency fT is defined as the frequency when the
current gain is 1.
Input current = G
Gv
C
J 
Output current = G
mv
g
vG here is ac signal
CGS is approximately equal to the
gate capacitance,  Z L Cox
So, at fT, 1
2 G
GS
T
G
m 

 v
C
f
v
g
GS
m
T
2 C
g
f


So,

CMOS Technology
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Four main CMOS technologies
– N-well process
– P-well process
– Twin-Tub process
– Silicon on Insulator

Detailed Mask Views
 Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well

n-Well Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate

Oxidation
 Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2

Photoresist
 Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
p substrate
SiO2
Photoresist

Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist
p substrate
SiO2
Photoresist

Etch
 Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist

Strip Photoresist
 Strip off remaining photoresist
– Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step
p substrate
SiO2

n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
 Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2

Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps
p substrate
n well

Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well

Polysilicon Patterning
 Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well

Self-Aligned Process
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well
contact
p substrate
n well

N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substrate
n well
n+ Diffusion

N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion
n well
p substrate
n+
n+ n+

N-diffusion cont.
 Strip off oxide to complete patterning step
n well
p substrate
n+
n+ n+

P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substrate
n well
n+
n+ n+
p+
p+
p+

Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Contact

Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal

73
CMOS Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

CMOS N-well process
An N-well process is also widely used
N-well
P-type substrate
N+ P+
P+ for P-substrate
contact) N+ (for N-
substrate contact)
Vdd Vss
Vin
Vout
P channel
Device
N channel
Device

Composite layout and cross-section view of n-well CMOS device
(excludes passivation and patterning of wire-bonding pads)

p-Well CMOS Process
- The substrate is N-Type. The N-Channel device is
built into a P-Type well within the parent N-Type
substrate. The P-channel device is built directly
on the substrate.
P-well
SiO2
N-type substrate

p-Well CMOS
p-well acts as substrate for nMOS devices.
P
N-type substrate
P+ N+
N+ for N-substrate
contact)
P+ (for P-substrate
contact)
Vdd Vss
Vin
Vout
P channel
Device N channel
Device

Twin-tub CMOS process
 Provide separate optimization of the n-type and p-type transistors
 Make it possible to optimize "Vt", "Body effect", and the "Gain" of n,
p devices, independently.
 Steps:
– Starting material: an n+ or p+ substrate with lightly doped ->
"epitaxial" or "epi" layer -> to protect "latch up"
– Epitaxy"
– Grow high-purity silicon layers of controlled thickness
– With accurately determined dopant concentrations
– Electrical properties are determined by the dopant and its
concentration in Si
 C. Process sequence
– Tub formation
– Thin-Oxide construction
– Source & drain implantations
– Contact cut definition
– Metallization
 Balanced performance of n and p devices can be constructed

Twin Tub Process cont..

Silicon on Insulator
A thin film of very lightly
doped n-type Si is grown over
insulator
Anisotropic etch is used to etch
away Si, except in the diffusion
area (n or p) is needed. Fig (b, c)
p-islands are formed by masking n-
islands with photo resist. A p-type
dopant (Boron) is then implanted.
P-islands are covered with photo
resist and n-type phosphorous is
implanted to form n-island

Silicon on Insulator Cont…
A thin oxide is grown by thermal
oxidation and a poly silicon film is
deposited over the oxide.
Poly silicon is patterned by
photo masking and then
etched.
N-channel device is formed by masking n-
islands and implanting n-type dopant
phosphorous. Poly silicon over the gate of p-
islands will block the dopants from the gate
P-channel device is formed by masking p-
islands and implanting p-type dopant Boron.
Poly silicon over the gate of n-islands will
block the dopants from the gate
Phosphorus glass or insulator such as SiO2
is deposited over the entire structure.

 Advantages of SOI
– Absence of wells results in denser transistor
structures and direct n to p connections can be done
– Lower substrate capacitance provides faster circuits
– No field inversion problem exists (insulating
Substrate)
– No latch up problem because of isolation between n
and p transistors by insulating substrate
– No body effect because no conducting substrate
– There is enhanced radiation tolerance.
 Disadvantages of SOI
– Absence of substrate diodes makes the input diffiult
to protect
– Coupling capacitance exists

VLSI- Unit I

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VLSI- Unit I