System on Chip

SoC Design
Subject code: 12EC129
By ,
` Swamy TN
Assit Prof, ECE dept
Dr. AIT, Bangalore

Unit 1
Motivation for SoC Design

Learning objectives
• Review of Moore’s law and CMOS Scaling,
• Benefits of system-on-chip integration in
terms of cost, power, and performance.
• Comparison of System-on-Board, System-on-
Chip, and System-in-Package.
• Typical goals in SoC design – cost reduction,
power reduction, design effort reduction,
performance maximization.
3Prof. Swamy TN, ECE, Dr.AIT3/9/2020

References
• Rao R. Tummala, Madhavan Swaminathan,
“Introduction to system on package sop-
Miniaturization of the Entire System”,
McGraw-Hill-2008.
• Sung- Mo Kang, Yusuf Leblebici, “CMOS Digital
Integrated Circuits”, Tata Mcgraw-hill, 3rd
Edition.

What is SoC ?
People A:
The VLSI manufacturing technology advances has made possible to put
millions of transistors on a single die. It enables designers to put systems-
on-a-chip that move everything from the board onto the chip eventually.
People B:
SoC is a high performance microprocessor, since we can program and
give instruction to the uP to do whatever you want to do.
People C:
SoC is the efforts to integrate heterogeneous or different types of silicon
IPs on to the same chip, like memory, uP, random logics, and analog
circuitry.
All of the above are partially right, but not very accurate!!!

What is SoC ?
SoC not only chip, but more on “system”.
SoC = Chip + Software + Integration
The SoC chip includes:
Embedded processor
ASIC Logics and analog circuitry
Embedded memory
The SoC Software includes:
OS, compiler, simulator, firmware, driver, protocol stackIntegrated
development environment (debugger, linker, ICE)Application interface
(C/C++, assembly)
The SoC Integration includes :
The whole system solution
Manufacture consultant
Technical Supporting 6Prof. Swamy TN, ECE, Dr.AIT3/9/2020

System on Chip interconnection
• AMBA (Advanced Microcontroller Bus
Architecture) is a collection of buses from ARM
for satisfying a range of different criteria.
• APB (Advanced Peripheral Bus): simple strobed-
access bus with minimal interface complexity.
Suitable for hosting peripherals.
• ASB (Advanced System Bus): a multimaster
synchronous system bus.
• AHB (Advanced High Performance Bus): a high-
throughput synchronous system backbone. Burst
transfers and split transactions.

SoC cores
• Cores are the basic building blocks
• Resuse: design productivity gap is to make
ASIC designs more standardized by reusing
segments of previously manufactured chips.
• These segments are known as “blocks”,
“macros”, “cores” or “cells”.(designed or
purchased form IP company)

System on Chip cores
• Soft Macro
• Firm Macro
• Hard Macro

Soft macro
• Soft macros are in synthesizable RTL.
• Soft macros are more flexible than firm or hard macros.
• Soft macros are not specific to any manufacturing process.
• Soft macros have the disadvantage of being somewhat
unpredictable in terms of performance, timing, area, or
power.
• Soft macros are editable and can contain standard cells,
hard macros, or other soft macros.

Firm macro
• Firm macros are in netlist format.
• Firm macros are optimized for
performance/area/power using a specific
fabrication technology.
• Firm macros are more flexible and portable
than hard macros.
• Firm macros are predictive of performance
and area than soft macros.

Hard macro
• Hard macros are generally in the form of hardware IPs (or
we termed it as hardwre IPs !).
• Hard macos are targeted for specific IC manufacturing
technology.
• Hard macros are block level designs which are silicon tested
and proved.
• Hard macros have been optimized for power or area or
timing.
• You have freedom to move, rotate, flip but you can't touch
anything inside hard macros.
• Very common example of hard macro is memory. It can be
any design which carries dedicated single functionality

Example of SOC
single chip DSL modem system on
chip

Example
SOC application of the internet era

Key customer requirements

SoC complexity

The integrated circuit(IC) era…
• Moore’s law

generations of IC’s

performance analysis of Technologies

MOS & related VLSI technology
• nMOS is preferred technology
– Design methodologies and design rules are easy
– Transition from nMOS to CMOS is easy
– For GaAs technology some arrangements in
relation to logic design are similar to those
employed in nMOS technology
– Therefore understanding the basis of nMOS
design will assist in layout of GaAs circuits.

Introduction to MOSFET scaling
• MOORE law
• Eg. 14.2 million transistors in pentium
processor.
• Scaling.
– The process of reducing vertical and horizontal
dimensions of MOSFET is called scaling.

Scaling example
• W, L, tox, junction depth,

MOSFET scaling trends

Benefits of scaling
– Increased component density
– Increased speed
– Reduction in power consumption
– Less cost per chip

Types of scaling
• Constant voltage scaling
• Constant field scaling

Constant field scaling
• Here MOSFET dimensions as well as supply
voltages are scaled by the same factor S.
• Full scaling: Scaling of supply voltages and
terminal voltages maintains the same electric
field, hence the name. BOTH VOLTAGES AND
DIMENSIONS ARE SCALED SIMULTANEOUSLY.

Benefits of constant field scaling
• Increased component density
• Increased speed
• Decreased cost

Impact of scaling on current Ids

Parameters before and after scaling
constant field

Constant voltage scaling
• Here geometrical dimension of the MOSFET
are scaled by scaling factor S while the supply
and terminal voltage remain constant.
• Partial scaling:
• Since only dimension is scaled.

Impact of voltage scaling on gate
oxide capacitance

Advantages of constant voltage
scaling
• Less delay
• Decreased cost
• More reliable

Parameters before and after scaling
constant voltage

Second order effects
• Channel-length Modulation
• Subthreshold Region
• Drain punchthrough
• Hot electrons(Impact ionization)
• Fowler-Nordheim Tunneling
• Mobility Variation

Channel-length modulation
• It is assumed that the carrier mobility is
constant, and do not take into account the
variations in channel length due to changes in
drain to source voltage, Vds.
• For long channel lengths, the channel
variations is of little consequence.
• As device are scaled down, the variation is
taken into consideration

Channel-length modulation….

Subthreshold region
• The cutoff region described by the equation
• Is referred as the subthreshold region
• Where Ids increases exponentially with Vds
and Vgs.
• Note: finite value of Ids may be used to
construct very low power circuits.

Drain Punchthrough
• When the drain is at a high enough voltage
w.r.t source
• The depletion region around the drain may
extend to the source
• Thus current flows irrespective of the gate
voltage.(even Vgs = 0)
• Used in I/O protection circuits(to limit the
voltages across internal circuit nodes)

Impact Ionization-Hot electrons
• When the gate of an MOS transistor is
reduced
• The electric field at the drain of a transistor in
saturation increases
• For submicron gate lengths, the field become
high that electrons get enough energy. Termed
as “HOT”
• This increases the substrate current.

Fowler-Nordheim Tunneling
• When the gate oxide is very thin, a current can
flow form gate to source or drain by electron
tunneling through the gate oxide given by

Mobility variation
• The mobility of carriers is given by

SOC Architecture
 Hardware:
 Analog: ADC, DAC, PLL, TxRx,
RF…etc.
 Digital: Processor, Interface,
Accelerator…etc.
 Storage: SRAM, DRAM, FLASH,
ROM…etc.
 Software: OS, Application
Prof. Swamy TN, ECE, Dr.AIT 423/9/2020

CISC vs RISC
CISC RISC
Complex instructions require
multiple cycles
Reduced instructions take 1 cycle
A large variety of addressing modes Relatively few addressing modes
Instructions are executed one at a
time
Uses pipelining to execute
instructions
Few general registers Many general registers
3/9/2020 43Prof. Swamy TN, ECE, Dr.AIT

PLL
• A phase-locked loop or phase lock loop (PLL)
is a control system that generates an output
signal whose phase is related to the phase of
an input signal.

Hardware Accelerators
• If the overall performance of a uniprocessor
system is too slow, additional hardware can be
used to speed up the system.
• This hardware is called hardware accelerator!
• The hardware accelerator is a component that
works together with the processor and executes
key functions much faster than the Processor.

Hardware Accelerators
• The hardware accelerator can be
implemented in
1. Application-specific integrated circuit.
• 2. Field-programmable gate array (FPGA).

Example-convergence in a mobile
handset

Example- SOC for high performance
audio

Example
SOC for digital control

SOC design challenge
• Reducing delay
• Reducing the development cost
• Time to market
• Reduction in power dissipation
• Testablity

The Benefits of SOC
• There are several benefits in integrating a large
digital system into a single integrated circuit .
• These include
– Lower cost per gate .
– Lower power consumption .
– Faster circuit operation .
– More reliable implementation .
– Smaller physical size .
– Greater design security .

The Drawbacks
• The principle drawbacks of SoC design are
associated with the design pressures imposed
on today’s engineers , such as :
– Time-to-market demands .
– Exponential fabrication cost .
– Increased system complexity .
– Increased verification requirements .

Architectures
• Von Neumann Architecture
• Harvard Architecture

Von Neumann Architecture
• It is named after
the mathematician and
early computer
scientist John Von
Neumann.
• The computer has single
storage system(memory)
for storing data as well as
program to be executed.
• Processor needs two
clock cycles to complete
an instruction.

Harvard Architecture
• The name is originated
from "Harvard Mark I" a
relay based old
computer.
• The computer has two
separate memories for
storing data and
program.
• Processor can complete
an instruction in one
cycle

Design gap

SOC design phase I
• SOC definition and challenges
• HW-SW codesign – Memory subsystem
definiton
• Chip package codesign

SOC definition and challenges

HW/SW codesign

Prof. Swamy TN, ECE, Dr.AIT
60
3/9/2020

Example
Memory subsystem

Why package is needed
• Delivers power to the Chip
• Transfers information into and out of the Chip
to the PCB
• Draws heat away from the Chip
• Protects the Chip from outside elements

Chip-package codesign
• There are two types of package
– Flip chip package
• Lower IR drop
• Higher performance
– Wire bond package
• More higher drop
• Lower performance

SOC design phase II
• SOC H/W-S/W codesign and architectural level
partitioning.
• SOC integration
• SOC verification

Technology scaling
• Explain moore’s law
• Benefits of scaling
– Increased component density
– Increased speed
– Reduction in power consumption
– Less cost per chip

Design for test
• Testing
– Logic Verification
– Silicon Debug
– Manufacturing Test
• Methods
– Boundary scan mode
– BIST

Boundary scan
Prof. Swamy TN, ECE, Dr.AIT 68
SerialData In
SerialData Out
PackageInterconnect
IOpad andBoundaryScan
Cell
CHIP A
CHIP B CHIP C
CHIP D
3/9/2020

Power dissipation trends

MOSFET capacitances
Prof. Swamy TN, ECE, Dr.AIT 70
• The MOS structure can be thought of as a parallel-plate
capacitor, with the top plate being the positive plate,
oxide being the dielectric, and Si substrate being the
negative plate. (We are assuming P-substrate.)
3/9/2020

Addressing design complexity
• Top down approach
• Bottom up approach
• Modularity
• Reusability(IP cores)
• Locality
– Reduce global wiring.

Design abstraction levels

Design planning
• Floor planning
• Size estimation
• Power estimation
• Timing estimation
• Routing estimation

Design closure
• SOC design closure is
the simultaneous
process of meeting the
speed, power
dissipation, area, signal
integrity, an
requirements of the
device, while at the
same time ensuring
that the critical time-to-
market goals are met.

Mixed signal Integration

comparison

Goals of SOC
• cost reduction
• power reduction
• design effort reduction
• performance maximization

Power reduction
• Disconnect inactive logic from supply in standby mode.
• Use thick oxide : suppresses gate leakage.
 Dual-Vt Storage Cells
 Low Vt for high performance
 High Vt for low leakage

Voltage Island Concept
 Trade off power for delay by running
functional blocks at different voltages
 Can use mix of Low and High Vt to
balance performance and leakage
 Switch off inactive blocks to reduce
leakage power
 Requires IP standards for power
management, clock gating, etc.
Power Management Unit
SWITCH SWITCH
Logic
Low VT
Logic
Vddo
Vdd1 Vdd2
IP1 IP2
Source from Bergamaschi

Conventional Power Management
Power
Manager
ON
IDLE STANDBY
RESTART
– STANDBY is off but with state retained with clocks stopped
– IDLE is a lower power mode with a slow clock running
– ON state is fully powered up at maximum clock frequency
• Conventional power management schemes manage the
transitions between defined power states
• Despite the changing software workload, system runs at
maximum performance while there is any work to be done

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