Spdas1 vlsibput


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Spdas1 vlsibput

  1. 1. <ul><li>VLSI </li></ul>
  2. 2. <ul><li>What is VLSI? </li></ul><ul><ul><li>“ Very Large Scale Integration” </li></ul></ul><ul><li>SSI – Small-Scale Integration (0-10 2 )---1960 </li></ul><ul><li>MSI – Medium-Scale Integration (10 2 -10 3 )---1967 </li></ul><ul><li>LSI – Large-Scale Integration (10 3 -10 5 )---1972 </li></ul><ul><li>VLSI – Very Large-Scale Integration (10 5 -10 7 )---1978 </li></ul><ul><li>ULSI – Ultra Large-Scale Integration (>=10 7 )---1989 </li></ul><ul><li>GSI _ Giant Scale Integration (>=10 9 )---2000 </li></ul><ul><li>*Where these are given as no of transistors. </li></ul>
  3. 3. Integration Level Trends Obligatory historical Moore’s law plot
  4. 5. <ul><li>Integrated Circuits/MEMs </li></ul><ul><ul><li>Hierarchy of various technology </li></ul></ul><ul><ul><li>Semiconductor process </li></ul></ul><ul><ul><li>Silicon </li></ul></ul><ul><ul><li>GaAs </li></ul></ul><ul><ul><li>Unipolar </li></ul></ul>Bipolar Unipolar Bipolar ECL TTL NMOS PMOS CMOS
  5. 6. <ul><li>Chips </li></ul><ul><li>Integrated circuits consist of: </li></ul><ul><ul><li>A small square or rectangular “die”, < 1mm thick </li></ul></ul><ul><ul><ul><li>Small die: 1.5 mm x 1.5 mm => 2.25 mm 2 </li></ul></ul></ul><ul><ul><ul><li>Large die: 15 mm x 15 mm => 225 mm 2 </li></ul></ul></ul><ul><ul><li>Larger die sizes mean: </li></ul></ul><ul><ul><ul><li>More logic, memory </li></ul></ul></ul><ul><ul><ul><li>Less volume </li></ul></ul></ul><ul><ul><ul><li>Less yield </li></ul></ul></ul><ul><ul><li>Dies are made from silicon (substrate) </li></ul></ul><ul><ul><ul><li>Substrate provides mechanical support and electrical common point </li></ul></ul></ul>
  6. 7. Advancements over the years <ul><li>© Intel 4004 Processor </li></ul><ul><li>Introduced in 1971 </li></ul><ul><li>2300 Transistors </li></ul><ul><li>108 KHz Clock </li></ul><ul><li>© Intel P4 Processor </li></ul><ul><li>Introduced in 2000 </li></ul><ul><li>40 Million Transistors </li></ul><ul><li>1.5GHz Clock </li></ul>
  7. 8. System Design Pyramid
  8. 9. • Photo-litho-graphy: lati n: light-stone-writing • Photolithography: an optical means for transferring patterns onto a substrate. • Patterns are first transferred to a photoresist layer . • Typically a wafer is about 8-10 inches in diameter. Individual ICs are placed inside it. Photolithography and Patterning
  9. 10. Photoresist is a liquid film that is spread out onto a substrate, exposed with a desired pattern, and developed into a selectively placed layer for subsequent processing. • Photolithography is a binary pattern transfer : there is no gray-scale, color, nor depth to the image.
  10. 14. <ul><li>Steps </li></ul><ul><li>Photo resist Coating (covering) </li></ul><ul><li>A light sensitive organic polymer (plastic) </li></ul><ul><li>Mask/ Reticle formation </li></ul><ul><li>Exposure to light (UV/X-RAY/E-BEAM) </li></ul>
  11. 17. WHAT IS A PHOTOMASK? Photomasks are high precision plates containing microscopic images of electronic circuits. Photomasks are made from very flat pieces of quartz or glass with a layer of chrome on one side. Etched in the chrome is a portion of an electronic circuit design. This circuit design on the mask is also called geometr y.
  12. 18. The Resist The first step is to coat the Si/SiO 2 wafer with a film of a light sensitive material, called a resist. A resist must also be capable of high fidelity recording of the pattern (resolution) and durable enough to survive later process steps Solvent Evaporates
  13. 21. Photolithography Energy - causes (photo)chemical reactions that modify resist dissolution rate Mask - blocks energy transmission to some areas of the resist Aligner - aligns mask to previously exposed layers of the overall design Resist - records the masked pattern of energy Energy Mask + Aligner Photoresist Wafer
  14. 22. Next Generation Lithography In 1996, five technology options were proposed for the 130 nm gate length technology: • X-ray proximity Lithography (XPL) • Extreme Ultraviolet (EUV) • Electron Projection Lithography (EPL) • Ion Projection Lithography (IPL) • Direct-write lithography (EBDW). These options were referred to as the next generation lithography.
  15. 24. MOSFET Design Rules <ul><li>Lambda based design Rule </li></ul><ul><li>Micron Rule </li></ul>
  16. 25. Minimum width and Spacing <ul><li>Layer Value </li></ul><ul><li>Poly 2L </li></ul><ul><li>Active 3L </li></ul><ul><li>N select 3L </li></ul><ul><li>Metal 3L </li></ul>
  17. 26. Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style.
  18. 27. <ul><li>Wiring Tracks </li></ul><ul><li>A wiring track is the space required for a wire </li></ul><ul><ul><li>4  width, 4  spacing from neighbor = 8  pitch </li></ul></ul><ul><li>Transistors also consume one wiring track </li></ul>
  19. 28. <ul><li>Well spacing </li></ul><ul><li>Wells must surround transistors by 6  </li></ul><ul><ul><li>Implies 12  between opposite transistor flavors </li></ul></ul><ul><ul><li>Leaves room for one wire track </li></ul></ul>
  20. 29. Basic Circuit Layout Stick Diagram Stick Diagrams Gnd V DD X X X X V DD Gnd
  21. 30. Layout Diagrams Stick Diagrams Gnd V DD X X X X V DD Gnd
  22. 31. <ul><li>Example: Inverter </li></ul>
  23. 32. MOSFET Arrays and AOI Gates A B C y x y x A B C
  24. 33. Parallel Connected MOS Patterning x y A B X X X A B x y
  25. 34. Alternate Layout Strategy A B x y X X X X x A B y
  26. 35. MOSFET Arrays and AOI Gates NAND2 Layout Vp Gnd Gnd Vp X X X X X
  27. 36. NOR2 Layout Vp Gnd Vp Gnd X X X X X
  28. 37. Stick Diagrams Power Ground B C Out A
  29. 38. Cells, Libraries, and Hierarchical Design <ul><li>Creation of a Cell Library </li></ul>Gnd X X X X X X X X V DD X
  30. 39. X X X X X X X X X V DD Gnd X
  31. 40. Gnd X X X X X X X X X V DD
  32. 41. <ul><li>Cell Placement </li></ul><ul><li>System Hierarchy (MOSFET-Gates-F/Fs-Registers-Networks-Systems) </li></ul><ul><li>Floorplans and Interconnect Wiring </li></ul><ul><li>Y= (# of Good Chips/Total No)*100% </li></ul><ul><li>Y=Yield </li></ul><ul><li>‘ Y’ depends on total area=A, and no of defects=D, </li></ul><ul><li>Y=e *100% </li></ul>
  33. 42. Interconnects <ul><li>Place and Route Algorithm. </li></ul><ul><li>Wiring Delay </li></ul><ul><li>td=kl 2 </li></ul><ul><li>l=length of inter connect. </li></ul>td