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Lec0 fab

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Lec0 fab

  1. 1. Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design
  2. 2. Fabrication and Layout Slide 2CMOS VLSI Design Introduction  Integrated circuits: many transistors on one chip. – Very Large Scale Integration (VLSI): very many  Metal Oxide Semiconductor (MOS) transistor – Fast, cheap, low-power transistors – Complementary: mixture of n- and p-type leads to less power  Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication  Rest of the course: How to build a good CMOS chip
  3. 3. Fabrication and Layout Slide 3CMOS VLSI Design Silicon Lattice  Transistors are built on a silicon substrate  Silicon is a Group IV material  Forms crystal lattice with bonds to four neighbors Si SiSi Si SiSi Si SiSi
  4. 4. Fabrication and Layout Slide 4CMOS VLSI Design Dopants  Silicon is a semiconductor  Pure silicon has no free carriers and conducts poorly  Adding dopants increases the conductivity  Group V: extra electron (n-type)  Group III: missing electron, called hole (p-type) As SiSi Si SiSi Si SiSi B SiSi Si SiSi Si SiSi - + + -
  5. 5. Fabrication and Layout Slide 5CMOS VLSI Design p-n Junctions  A junction between p-type and n-type semiconductor forms a diode.  Current flows only in one direction p-type n-type anode cathode
  6. 6. Fabrication and Layout Slide 6CMOS VLSI Design nMOS Transistor  Four terminals: gate, source, drain, body  Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor – Even though gate is no longer made of metal n+ p GateSource Drain bulk Si SiO2 Polysilicon n+
  7. 7. Fabrication and Layout Slide 7CMOS VLSI Design nMOS Operation  Body is commonly tied to ground (0 V)  When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 0 S
  8. 8. Fabrication and Layout Slide 8CMOS VLSI Design nMOS Operation  When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 1 S
  9. 9. Fabrication and Layout Slide 9CMOS VLSI Design pMOS Transistor  Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior SiO2 n GateSource Drain bulk Si Polysilicon p+ p+
  10. 10. Fabrication and Layout Slide 10CMOS VLSI Design Power Supply Voltage  GND = 0 V  In 1980’s, VDD = 5V  VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power  VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
  11. 11. Fabrication and Layout Slide 11CMOS VLSI Design Transistors as Switches  We can view MOS transistors as electrically controlled switches  Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
  12. 12. Fabrication and Layout Slide 12CMOS VLSI Design CMOS Inverter A Y 0 1 VDD A Y GND A Y
  13. 13. Fabrication and Layout Slide 13CMOS VLSI Design CMOS Inverter A Y 0 1 0 VDD A=1 Y=0 GND ON OFF A Y
  14. 14. Fabrication and Layout Slide 14CMOS VLSI Design CMOS Inverter A Y 0 1 1 0 VDD A=0 Y=1 GND OFF ON A Y
  15. 15. Fabrication and Layout Slide 15CMOS VLSI Design CMOS NAND Gate A B Y 0 0 0 1 1 0 1 1 A B Y
  16. 16. Fabrication and Layout Slide 16CMOS VLSI Design CMOS NAND Gate A B Y 0 0 1 0 1 1 0 1 1 A=0 B=0 Y=1 OFF ON ON OFF
  17. 17. Fabrication and Layout Slide 17CMOS VLSI Design CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 A=0 B=1 Y=1 OFF OFF ON ON
  18. 18. Fabrication and Layout Slide 18CMOS VLSI Design CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 A=1 B=0 Y=1 ON ON OFF OFF
  19. 19. Fabrication and Layout Slide 19CMOS VLSI Design CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A=1 B=1 Y=0 ON OFF OFF ON
  20. 20. Fabrication and Layout Slide 20CMOS VLSI Design CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y
  21. 21. Fabrication and Layout Slide 21CMOS VLSI Design 3-input NAND Gate  Y pulls low if ALL inputs are 1  Y pulls high if ANY input is 0
  22. 22. Fabrication and Layout Slide 22CMOS VLSI Design 3-input NAND Gate  Y pulls low if ALL inputs are 1  Y pulls high if ANY input is 0 A B Y C
  23. 23. Fabrication and Layout Slide 23CMOS VLSI Design CMOS Fabrication  CMOS transistors are fabricated on silicon wafer  Lithography process similar to printing press  On each step, different materials are deposited or etched  Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
  24. 24. Fabrication and Layout Slide 24CMOS VLSI Design Inverter Cross-section  Typically use p-type substrate for nMOS transistor – Requires n-well for body of pMOS transistors – Several alternatives: SOI, twin-tub, etc. n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
  25. 25. Fabrication and Layout Slide 25CMOS VLSI Design Well and Substrate Taps  Substrate must be tied to GND and n-well to VDD  Metal to lightly-doped semiconductor forms poor connection called Shottky Diode  Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND VDD n+p+ substrate tap well tap n+ p+
  26. 26. Fabrication and Layout Slide 26CMOS VLSI Design Inverter Mask Set  Transistors and wires are defined by masks  Cross-section taken along dashed line GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
  27. 27. Fabrication and Layout Slide 27CMOS VLSI Design Detailed Mask Views  Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
  28. 28. Fabrication and Layout Slide 28CMOS VLSI Design Fabrication Steps  Start with blank wafer  Build inverter from the bottom up  First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 p substrate
  29. 29. Fabrication and Layout Slide 29CMOS VLSI Design Oxidation  Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace p substrate SiO2
  30. 30. Fabrication and Layout Slide 30CMOS VLSI Design Photoresist  Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light p substrate SiO2 Photoresist
  31. 31. Fabrication and Layout Slide 31CMOS VLSI Design Lithography  Expose photoresist through n-well mask  Strip off exposed photoresist p substrate SiO2 Photoresist
  32. 32. Fabrication and Layout Slide 32CMOS VLSI Design Etch  Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!!  Only attacks oxide where resist has been exposed p substrate SiO2 Photoresist
  33. 33. Fabrication and Layout Slide 33CMOS VLSI Design Strip Photoresist  Strip off remaining photoresist – Use mixture of acids called piranah etch  Necessary so resist doesn’t melt in next step p substrate SiO2
  34. 34. Fabrication and Layout Slide 34CMOS VLSI Design n-well  n-well is formed with diffusion or ion implantation  Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si  Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si n well SiO2
  35. 35. Fabrication and Layout Slide 35CMOS VLSI Design Strip Oxide  Strip off the remaining oxide using HF  Back to bare wafer with n-well  Subsequent steps involve similar series of steps p substrate n well
  36. 36. Fabrication and Layout Slide 36CMOS VLSI Design Polysilicon  Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers)  Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Thin gate oxide Polysilicon p substrate n well
  37. 37. Fabrication and Layout Slide 37CMOS VLSI Design Polysilicon Patterning  Use same lithography process to pattern polysilicon Polysilicon p substrate Thin gate oxide Polysilicon n well
  38. 38. Fabrication and Layout Slide 38CMOS VLSI Design Self-Aligned Process  Use oxide and masking to expose where n+ dopants should be diffused or implanted  N-diffusion forms nMOS source, drain, and n-well contact p substrate n well
  39. 39. Fabrication and Layout Slide 39CMOS VLSI Design N-diffusion  Pattern oxide and form n+ regions  Self-aligned process where gate blocks diffusion  Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing p substrate n well n+ Diffusion
  40. 40. Fabrication and Layout Slide 40CMOS VLSI Design N-diffusion  Historically dopants were diffused  Usually ion implantation today  But regions are still called diffusion n well p substrate n+n+ n+
  41. 41. Fabrication and Layout Slide 41CMOS VLSI Design N-diffusion  Strip off oxide to complete patterning step n well p substrate n+n+ n+
  42. 42. Fabrication and Layout Slide 42CMOS VLSI Design P-Diffusion  Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p substrate n well n+n+ n+p+p+p+
  43. 43. Fabrication and Layout Slide 43CMOS VLSI Design Contacts  Now we need to wire together the devices  Cover chip with thick field oxide  Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+n+ n+p+p+p+ Contact
  44. 44. Fabrication and Layout Slide 44CMOS VLSI Design Metallization  Sputter on aluminum over whole wafer  Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+n+ n+p+p+p+ Metal
  45. 45. Fabrication and Layout Slide 45CMOS VLSI Design Layout  Chips are specified with set of masks  Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)  Feature size f = distance between source and drain – Set by minimum width of polysilicon  Feature size improves 30% every 3 years or so  Normalize for feature size when describing design rules  Express rules in terms of λ = f/2 – E.g. λ = 0.3 µm in 0.6 µm process
  46. 46. Fabrication and Layout Slide 46CMOS VLSI Design Simplified Design Rules  Conservative rules to get you started
  47. 47. Fabrication and Layout Slide 47CMOS VLSI Design Inverter Layout  Transistor dimensions specified as Width / Length – Minimum size is 4λ / 2λ, sometimes called 1 unit – For 0.6 µm process, W=1.2 µm, L=0.6 µm
  48. 48. Fabrication and Layout Slide 48CMOS VLSI Design Summary  MOS Transistors are stack of gate, oxide, silicon  Can be viewed as electrically controlled switches  Build logic gates out of switches  Draw masks to specify layout of transistors  Now you know everything necessary to start designing schematics and layout for a simple chip!

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