SlideShare a Scribd company logo
1 of 9
EC8095-VLSI DESIGN
INTRODUCTION AND FUNDAMENTALS
Prepared by
Mrs.T.G.RAMABHARATHI
ASSISTANT PROFESSOR
ECE DEPARTMENT
KARPAGAM INSTITUTE OF TECHNOLOGY,COIMBATORE.
UNIT-I INTRODUCTION TO MOS TRANSISTOR
• An MOS (Metal-Oxide-Silicon) structure is created by superimposing several layers
of conducting, insulating, and transistor forming materials.
• After a series of processing steps, a typical structure might consists of levels
called diffusion, polysilicon, and metal that are separated by insulating layers.
• CMOS technology provides two types of transistors, an n-type transistor (n MOS)
and a p-type transistor (p MOS). These are fabricated in silicon by using either
negatively doped silicon that is rich in electrons (negatively charged) or positively
doped silicon that is rich in holes (the dual of electrons and positively charged).
• For the n-transistor, the structure consists of a section of p-type silicon separating
two diffused areas of n-type silicon.
• The area separating the n regions is capped with a sandwich consisting of an
insulator and a conducting electrode called the GATE. Similarly, for the p-
transistor the structure consists of a section of n-type silicon separating two p-type
diffused areas.
Contd…
• The p-transistor also has a gate electrode. The gate is a control input and it affects
the flow of electrical current between the drain and source. The drain and source
may be viewed as two switched terminals.
• The design considerations for a simple inverter to address the synthesis of arbitrary
digital gates such as NOR, NAND and XOR is discussed.
• The focus is on combinational logic (or non-regenerative) circuits; this is, circuits
that have the property that at any point in time, the output of the circuit is related to
its current input signals by some Boolean expression (assuming that the transients
through the logic gates have settled).
UNIT II COMBINATIONAL MOS LOGIC CIRCUITS
• This is in contrast to another class of circuits, known as sequential or
regenerative, for which the output is not only a function of the current input
data, but also of previous values of the input signals.
• This is accomplished by connecting one or more outputs intentionally back
to some inputs. Consequently, the circuit “remembers” past events and has
a sense of history.
• A sequential circuit includes a combinational logic portion and a module that
holds the state. Example circuits are registers, counters, oscillators, and
memory.
Contd…
• There are numerous circuit styles to implement a given logic function. As
with the inverter, the common design metrics by which a gate is evaluated
are area, speed, energy and power.
• Depending on the application, the emphasis will be on different metrics. For
instance, the switching speed of digital circuits is the primary metric in a
high-performance processor, while it is energy dissipation in a battery
operated circuit.
• In addition to these metrics, robustness to noise and reliability are also very
important considerations. We will see that certain logic styles can
significantly improve performance, but are more sensitive to noise.
• Recently, power dissipation has also become a very important requirement
and significant emphasis is placed on understanding the sources of power
and approaches to deal with power.
UNIT III SEQUENTIAL CIRCUIT DESIGN
• The design of a synchronous sequential circuit starts from a set of
specifications and culminates in a logic diagram or a list of Boolean
functions from which a logic diagram can be obtained.
• In contrast to a combinational logic, which is fully specified by a truth
table, a sequential circuit requires a state table for its specification.
The first step in the design of sequential circuits is to obtain a state
table or an equivalence representation, such as a state diagram.
UNIT IV-DESIGN OF ARITHMETIC BUILDING
BLOCKS AND SUBSYSTEM
• This Unit deals with Arithmetic unit - Bit-sliced data path (adder ,
multiplier, shifter, comparator, etc.) and Memory - RAM, ROM,
Buffers, Shift registers.
• A synchronous sequential circuit is made up of flip-flops and
combinational gates. The design of the circuit consists of
choosing the flip-flops and then finding the combinational
structure which, together with the flip-flops, produces a circuit
that fulfils the required specifications. The number of flip-flops is
determined from the number of states needed in the circuit.
UNIT-V IMPLEMENTATION
STRATEGIES
• This unit provides the basic concept of the technologies available in the
Integrated Circuits (ICs). Improvements in Large Scale Integration (VLSI)
technology have brought chips with millions of transistors into our offices
and homes.
• The chips may also be designed for the own applications and these chips
are called Application Specific Integrated circuits (ASICs).
• ASIC design methodology use chips with array of prefabricated gates (gate
arrays) or chips based on libraries of standard function cells (standard cell
design).
• Full custom IC have maximum density and performance for high-volume
standard products. Application Specific Standard Products (ASSPs)
incorporated the value added features for specific market segments such as
complete controllers for workstations.
Thank you

More Related Content

What's hot

What's hot (20)

Short Channel Effect In MOSFET
Short Channel Effect In MOSFETShort Channel Effect In MOSFET
Short Channel Effect In MOSFET
 
Architecture of 8051
Architecture of 8051Architecture of 8051
Architecture of 8051
 
Power dissipation cmos
Power dissipation cmosPower dissipation cmos
Power dissipation cmos
 
1st Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers
1st Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers1st Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers
1st Semester M Tech CMOS VLSI Design (Dec-2013) Question Papers
 
Sequential cmos logic circuits
Sequential cmos logic circuitsSequential cmos logic circuits
Sequential cmos logic circuits
 
Lambda design rule
Lambda design ruleLambda design rule
Lambda design rule
 
Cmos design
Cmos designCmos design
Cmos design
 
Embedded System
Embedded System Embedded System
Embedded System
 
Mosfet
MosfetMosfet
Mosfet
 
Unit no. 5 cmos logic design
Unit no. 5 cmos logic designUnit no. 5 cmos logic design
Unit no. 5 cmos logic design
 
Architecture of 8085 microprocessor
Architecture of 8085 microprocessorArchitecture of 8085 microprocessor
Architecture of 8085 microprocessor
 
Dynamic logic circuits
Dynamic logic circuitsDynamic logic circuits
Dynamic logic circuits
 
CMOS
CMOS CMOS
CMOS
 
Microprocessor & microcontroller
Microprocessor & microcontroller Microprocessor & microcontroller
Microprocessor & microcontroller
 
Successive approximation adc
Successive approximation adcSuccessive approximation adc
Successive approximation adc
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL  Introduction to FPGA, VHDL
Introduction to FPGA, VHDL
 
CMOS TG
CMOS TGCMOS TG
CMOS TG
 
Nyquist criterion for distortion less baseband binary channel
Nyquist criterion for distortion less baseband binary channelNyquist criterion for distortion less baseband binary channel
Nyquist criterion for distortion less baseband binary channel
 
CMOS Logic
CMOS LogicCMOS Logic
CMOS Logic
 
LOW POWER DESIGN VLSI
LOW POWER DESIGN VLSILOW POWER DESIGN VLSI
LOW POWER DESIGN VLSI
 

Similar to Vlsi design

UNIT-4-Logic styles for low power_part_2.ppt
UNIT-4-Logic styles for low power_part_2.pptUNIT-4-Logic styles for low power_part_2.ppt
UNIT-4-Logic styles for low power_part_2.pptRavi Selvaraj
 
VLSI unit 1 Technology - S.ppt
VLSI unit 1 Technology - S.pptVLSI unit 1 Technology - S.ppt
VLSI unit 1 Technology - S.pptindrajeetPatel22
 
unit 1vlsi notes.pdf
unit 1vlsi notes.pdfunit 1vlsi notes.pdf
unit 1vlsi notes.pdfAcademicICECE
 
Silicon to software share
Silicon to software shareSilicon to software share
Silicon to software shareNarendra Patel
 
SISTec Microelectronics VLSI design
SISTec Microelectronics VLSI designSISTec Microelectronics VLSI design
SISTec Microelectronics VLSI designDr. Ravi Mishra
 
Digital standard cell library Design flow
Digital standard cell library Design flowDigital standard cell library Design flow
Digital standard cell library Design flowijsrd.com
 
Digital VLSI Design : Introduction
Digital VLSI Design : IntroductionDigital VLSI Design : Introduction
Digital VLSI Design : IntroductionUsha Mehta
 
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptxUNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptx8885684828
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
 
Linear Integrated Circuits -LIC!
Linear Integrated Circuits -LIC!Linear Integrated Circuits -LIC!
Linear Integrated Circuits -LIC!PRABHAHARAN429
 
Lecture20 asic back_end_design
Lecture20 asic back_end_designLecture20 asic back_end_design
Lecture20 asic back_end_designHung Nguyen
 
Data Communications and Optical Network - Forouzan
Data Communications and Optical Network - ForouzanData Communications and Optical Network - Forouzan
Data Communications and Optical Network - ForouzanPradnya Saval
 
IRJET- A Novel Design of Flip Flop and its Application in Up Counter
IRJET-  	  A Novel Design of Flip Flop and its Application in Up CounterIRJET-  	  A Novel Design of Flip Flop and its Application in Up Counter
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
 
120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx
120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx
120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptxHamadaElabadla
 
Implementation of quantum gates using verilog
Implementation of quantum gates using verilogImplementation of quantum gates using verilog
Implementation of quantum gates using verilogShashank Kumar
 
Bicmos Technology - Overview
Bicmos Technology - OverviewBicmos Technology - Overview
Bicmos Technology - OverviewAyush Mittal
 

Similar to Vlsi design (20)

UNIT-4-Logic styles for low power_part_2.ppt
UNIT-4-Logic styles for low power_part_2.pptUNIT-4-Logic styles for low power_part_2.ppt
UNIT-4-Logic styles for low power_part_2.ppt
 
VLSI unit 1 Technology - S.ppt
VLSI unit 1 Technology - S.pptVLSI unit 1 Technology - S.ppt
VLSI unit 1 Technology - S.ppt
 
unit 1vlsi notes.pdf
unit 1vlsi notes.pdfunit 1vlsi notes.pdf
unit 1vlsi notes.pdf
 
Silicon to software share
Silicon to software shareSilicon to software share
Silicon to software share
 
SISTec Microelectronics VLSI design
SISTec Microelectronics VLSI designSISTec Microelectronics VLSI design
SISTec Microelectronics VLSI design
 
Digital standard cell library Design flow
Digital standard cell library Design flowDigital standard cell library Design flow
Digital standard cell library Design flow
 
Digital VLSI Design : Introduction
Digital VLSI Design : IntroductionDigital VLSI Design : Introduction
Digital VLSI Design : Introduction
 
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptxUNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
UNIT-1 VLSID-MREC-ECE-Dr.TM.pptx
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)
 
Linear Integrated Circuits -LIC!
Linear Integrated Circuits -LIC!Linear Integrated Circuits -LIC!
Linear Integrated Circuits -LIC!
 
Lecture20 asic back_end_design
Lecture20 asic back_end_designLecture20 asic back_end_design
Lecture20 asic back_end_design
 
Data Communications and Optical Network - Forouzan
Data Communications and Optical Network - ForouzanData Communications and Optical Network - Forouzan
Data Communications and Optical Network - Forouzan
 
IRJET- A Novel Design of Flip Flop and its Application in Up Counter
IRJET-  	  A Novel Design of Flip Flop and its Application in Up CounterIRJET-  	  A Novel Design of Flip Flop and its Application in Up Counter
IRJET- A Novel Design of Flip Flop and its Application in Up Counter
 
120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx
120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx
120190675 - Hamada Hossam El abadla - Appendix A- 10-2-2023.pptx
 
basic vlsi ppt
basic vlsi pptbasic vlsi ppt
basic vlsi ppt
 
M Tech New Syllabus(2012)
M Tech New Syllabus(2012)M Tech New Syllabus(2012)
M Tech New Syllabus(2012)
 
Full IC Flow.docx
Full IC Flow.docxFull IC Flow.docx
Full IC Flow.docx
 
Implementation of quantum gates using verilog
Implementation of quantum gates using verilogImplementation of quantum gates using verilog
Implementation of quantum gates using verilog
 
Ijetr011811
Ijetr011811Ijetr011811
Ijetr011811
 
Bicmos Technology - Overview
Bicmos Technology - OverviewBicmos Technology - Overview
Bicmos Technology - Overview
 

Recently uploaded

Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...
Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...
Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...NETWAYS
 
Motivation and Theory Maslow and Murray pdf
Motivation and Theory Maslow and Murray pdfMotivation and Theory Maslow and Murray pdf
Motivation and Theory Maslow and Murray pdfakankshagupta7348026
 
Night 7k Call Girls Noida Sector 128 Call Me: 8448380779
Night 7k Call Girls Noida Sector 128 Call Me: 8448380779Night 7k Call Girls Noida Sector 128 Call Me: 8448380779
Night 7k Call Girls Noida Sector 128 Call Me: 8448380779Delhi Call girls
 
OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...
OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...
OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...NETWAYS
 
No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...
No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...
No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...Sheetaleventcompany
 
SaaStr Workshop Wednesday w: Jason Lemkin, SaaStr
SaaStr Workshop Wednesday w: Jason Lemkin, SaaStrSaaStr Workshop Wednesday w: Jason Lemkin, SaaStr
SaaStr Workshop Wednesday w: Jason Lemkin, SaaStrsaastr
 
Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...
Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...
Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...NETWAYS
 
George Lever - eCommerce Day Chile 2024
George Lever -  eCommerce Day Chile 2024George Lever -  eCommerce Day Chile 2024
George Lever - eCommerce Day Chile 2024eCommerce Institute
 
Philippine History cavite Mutiny Report.ppt
Philippine History cavite Mutiny Report.pptPhilippine History cavite Mutiny Report.ppt
Philippine History cavite Mutiny Report.pptssuser319dad
 
Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...
Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...
Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...Kayode Fayemi
 
VVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara Services
VVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara ServicesVVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara Services
VVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara ServicesPooja Nehwal
 
Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...
Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...
Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...Krijn Poppe
 
Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...
Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...
Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...Hasting Chen
 
ANCHORING SCRIPT FOR A CULTURAL EVENT.docx
ANCHORING SCRIPT FOR A CULTURAL EVENT.docxANCHORING SCRIPT FOR A CULTURAL EVENT.docx
ANCHORING SCRIPT FOR A CULTURAL EVENT.docxNikitaBankoti2
 
OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...
OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...
OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...NETWAYS
 
CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...
CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...
CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...henrik385807
 
call girls in delhi malviya nagar @9811711561@
call girls in delhi malviya nagar @9811711561@call girls in delhi malviya nagar @9811711561@
call girls in delhi malviya nagar @9811711561@vikas rana
 
Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...
Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...
Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...Pooja Nehwal
 
CTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdf
CTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdfCTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdf
CTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdfhenrik385807
 
Open Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdf
Open Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdfOpen Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdf
Open Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdfhenrik385807
 

Recently uploaded (20)

Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...
Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...
Open Source Camp Kubernetes 2024 | Running WebAssembly on Kubernetes by Alex ...
 
Motivation and Theory Maslow and Murray pdf
Motivation and Theory Maslow and Murray pdfMotivation and Theory Maslow and Murray pdf
Motivation and Theory Maslow and Murray pdf
 
Night 7k Call Girls Noida Sector 128 Call Me: 8448380779
Night 7k Call Girls Noida Sector 128 Call Me: 8448380779Night 7k Call Girls Noida Sector 128 Call Me: 8448380779
Night 7k Call Girls Noida Sector 128 Call Me: 8448380779
 
OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...
OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...
OSCamp Kubernetes 2024 | Zero-Touch OS-Infrastruktur für Container und Kubern...
 
No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...
No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...
No Advance 8868886958 Chandigarh Call Girls , Indian Call Girls For Full Nigh...
 
SaaStr Workshop Wednesday w: Jason Lemkin, SaaStr
SaaStr Workshop Wednesday w: Jason Lemkin, SaaStrSaaStr Workshop Wednesday w: Jason Lemkin, SaaStr
SaaStr Workshop Wednesday w: Jason Lemkin, SaaStr
 
Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...
Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...
Open Source Camp Kubernetes 2024 | Monitoring Kubernetes With Icinga by Eric ...
 
George Lever - eCommerce Day Chile 2024
George Lever -  eCommerce Day Chile 2024George Lever -  eCommerce Day Chile 2024
George Lever - eCommerce Day Chile 2024
 
Philippine History cavite Mutiny Report.ppt
Philippine History cavite Mutiny Report.pptPhilippine History cavite Mutiny Report.ppt
Philippine History cavite Mutiny Report.ppt
 
Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...
Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...
Governance and Nation-Building in Nigeria: Some Reflections on Options for Po...
 
VVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara Services
VVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara ServicesVVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara Services
VVIP Call Girls Nalasopara : 9892124323, Call Girls in Nalasopara Services
 
Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...
Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...
Presentation for the Strategic Dialogue on the Future of Agriculture, Brussel...
 
Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...
Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...
Re-membering the Bard: Revisiting The Compleat Wrks of Wllm Shkspr (Abridged)...
 
ANCHORING SCRIPT FOR A CULTURAL EVENT.docx
ANCHORING SCRIPT FOR A CULTURAL EVENT.docxANCHORING SCRIPT FOR A CULTURAL EVENT.docx
ANCHORING SCRIPT FOR A CULTURAL EVENT.docx
 
OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...
OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...
OSCamp Kubernetes 2024 | A Tester's Guide to CI_CD as an Automated Quality Co...
 
CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...
CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...
CTAC 2024 Valencia - Sven Zoelle - Most Crucial Invest to Digitalisation_slid...
 
call girls in delhi malviya nagar @9811711561@
call girls in delhi malviya nagar @9811711561@call girls in delhi malviya nagar @9811711561@
call girls in delhi malviya nagar @9811711561@
 
Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...
Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...
Navi Mumbai Call Girls Service Pooja 9892124323 Real Russian Girls Looking Mo...
 
CTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdf
CTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdfCTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdf
CTAC 2024 Valencia - Henrik Hanke - Reduce to the max - slideshare.pdf
 
Open Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdf
Open Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdfOpen Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdf
Open Source Strategy in Logistics 2015_Henrik Hankedvz-d-nl-log-conference.pdf
 

Vlsi design

  • 1. EC8095-VLSI DESIGN INTRODUCTION AND FUNDAMENTALS Prepared by Mrs.T.G.RAMABHARATHI ASSISTANT PROFESSOR ECE DEPARTMENT KARPAGAM INSTITUTE OF TECHNOLOGY,COIMBATORE.
  • 2. UNIT-I INTRODUCTION TO MOS TRANSISTOR • An MOS (Metal-Oxide-Silicon) structure is created by superimposing several layers of conducting, insulating, and transistor forming materials. • After a series of processing steps, a typical structure might consists of levels called diffusion, polysilicon, and metal that are separated by insulating layers. • CMOS technology provides two types of transistors, an n-type transistor (n MOS) and a p-type transistor (p MOS). These are fabricated in silicon by using either negatively doped silicon that is rich in electrons (negatively charged) or positively doped silicon that is rich in holes (the dual of electrons and positively charged). • For the n-transistor, the structure consists of a section of p-type silicon separating two diffused areas of n-type silicon. • The area separating the n regions is capped with a sandwich consisting of an insulator and a conducting electrode called the GATE. Similarly, for the p- transistor the structure consists of a section of n-type silicon separating two p-type diffused areas.
  • 3. Contd… • The p-transistor also has a gate electrode. The gate is a control input and it affects the flow of electrical current between the drain and source. The drain and source may be viewed as two switched terminals. • The design considerations for a simple inverter to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR is discussed. • The focus is on combinational logic (or non-regenerative) circuits; this is, circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled).
  • 4. UNIT II COMBINATIONAL MOS LOGIC CIRCUITS • This is in contrast to another class of circuits, known as sequential or regenerative, for which the output is not only a function of the current input data, but also of previous values of the input signals. • This is accomplished by connecting one or more outputs intentionally back to some inputs. Consequently, the circuit “remembers” past events and has a sense of history. • A sequential circuit includes a combinational logic portion and a module that holds the state. Example circuits are registers, counters, oscillators, and memory.
  • 5. Contd… • There are numerous circuit styles to implement a given logic function. As with the inverter, the common design metrics by which a gate is evaluated are area, speed, energy and power. • Depending on the application, the emphasis will be on different metrics. For instance, the switching speed of digital circuits is the primary metric in a high-performance processor, while it is energy dissipation in a battery operated circuit. • In addition to these metrics, robustness to noise and reliability are also very important considerations. We will see that certain logic styles can significantly improve performance, but are more sensitive to noise. • Recently, power dissipation has also become a very important requirement and significant emphasis is placed on understanding the sources of power and approaches to deal with power.
  • 6. UNIT III SEQUENTIAL CIRCUIT DESIGN • The design of a synchronous sequential circuit starts from a set of specifications and culminates in a logic diagram or a list of Boolean functions from which a logic diagram can be obtained. • In contrast to a combinational logic, which is fully specified by a truth table, a sequential circuit requires a state table for its specification. The first step in the design of sequential circuits is to obtain a state table or an equivalence representation, such as a state diagram.
  • 7. UNIT IV-DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM • This Unit deals with Arithmetic unit - Bit-sliced data path (adder , multiplier, shifter, comparator, etc.) and Memory - RAM, ROM, Buffers, Shift registers. • A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of the circuit consists of choosing the flip-flops and then finding the combinational structure which, together with the flip-flops, produces a circuit that fulfils the required specifications. The number of flip-flops is determined from the number of states needed in the circuit.
  • 8. UNIT-V IMPLEMENTATION STRATEGIES • This unit provides the basic concept of the technologies available in the Integrated Circuits (ICs). Improvements in Large Scale Integration (VLSI) technology have brought chips with millions of transistors into our offices and homes. • The chips may also be designed for the own applications and these chips are called Application Specific Integrated circuits (ASICs). • ASIC design methodology use chips with array of prefabricated gates (gate arrays) or chips based on libraries of standard function cells (standard cell design). • Full custom IC have maximum density and performance for high-volume standard products. Application Specific Standard Products (ASSPs) incorporated the value added features for specific market segments such as complete controllers for workstations.