The document describes Katrina Little's design of a multi-function gate that can perform the logic functions of AND, OR, NOR, and NAND. The gate uses two data inputs (A and B) and two operation selection lines (X and Y) to determine which function to perform. Katrina presents the design methodology including truth tables, a Karnaugh map to simplify the function, and a Verilog implementation. She then outlines a test plan to simulate the design in a schematic capture tool and verify the physical implementation on a BASYS1 FPGA board matches the expected output.

1. Katrina Little
Experiment #3:
Multi-Function Gate

2. Katrina Little
Experiment #3
OBJECTIVES:
 Design a Multi-Function gate using Xilinx’s FPGA design tools and to document
the design.
 Design, simulate, and implement the multi-function gate to the BASYS(1) FPGA
board.
EQUIPMENT LIST:
 FPGA BASYS1 board
 Xilinx ISE program
 Flash Drive
 BIT file
BLOCK DIAGRAM:
DESIGN SPECIFICATION PLAN:
The idea is to design a multi-function gate that will have sets of inputs, and one output
F. The function F will be instructed to perform four different logic operations. A and B
are the data inputs. X and Y control what the gate will do. X and Y are the operation
selection lines.
Multi-Function
Gate
A
B
F
FIGURE(1)
YX

3. Katrina Little
Experiment #3
DESIGN METHODOLOGY
A and B tell the gate what operation to perform. If A and B both are 0, the gate will act
as an and gate. If A=0, B=1, the gate will operate as or. If A=1, B=0, the gate will
operate as NOR. If A and B are both 1, the gate operates as NAND. Refer to figure 2.
AB XY XY AND NAND XY OR NOR
00 AND 00 0 1 00 0 1
01 OR 01 0 1 01 1 0
10 NOR 10 0 1 10 1 0
11 NAND 11 1 0 11 1 0
X and Y depend upon what A and B are doing. The truth tables for AND, NAND, OR,
and NOR can be seen in figures 3 and 4. The three above figures can be condensed
into a lengthy truth table as shown below in figure 5.
AB XY Z
00 00 0
00 01 0
00 10 0
00 11 1
01 00 0
01 01 1
01 10 1
01 11 1
10 00 1
10 01 0
10 10 0
10 11 0
11 00 1
11 01 1
11 10 1
11 11 0
Figure 2 Figure 3 Figure 4
Figure 5 (left)
Full truth table of the multi- function gate.
Notice that the values depicted in red
AB=00, therefore XY will act as an AND
gate. For the blue values AB=01, therefore
XY will act as an OR gate. For the yellow
values, AB =10, therefore XY acts as a NOR
gate. For the purple values AB=11,
therefore, XY acts as a NAND gate. Refer
back to figure to regarding The color.
Coordination. The output Z follows the truth
tables depicted in figures 3 & 4.

4. Katrina Little
Experiment #3
It can easily be seen how the truth table can get rather complicated. A Karnaugh Map
would be a more convenient way to represent the multi-function gate.
By using the ones on the table, the function can be written as a sum of products
(SOPS). To do this you need ABXY to multiply out to equal 1. Therefore, the un-
simplified equation for f is:
F = AX’Y’ + BX’Y’+ A’XY + BXY’
0 0
0
0 0
0 0
0
1
1 1
11
1
1
1
ab
xy
00
01
11
10
10
00 01 10 11
11 Figure 6
Karnaugh map of the multi-function
gate. To write the function pairs of
ones must be grouped together.
Note:
For orange: B is changing ignore it.
For purple: A is changing, ignore it.
For pink: B is changing, ignore it
For green: A is changing, ignore it.

5. Katrina Little
Experiment #3
DETAILED SCHEMATIC DIAGRAM:
INPUT/OUTPUT SWITCH PIN
#
LED
#
A SW0 38
B SW1 36
X SW6 10
Y SW7 6
F 2 7
Figure 8
A
Y
X
B
Y
X
A
Y
X
B
Y
X
F
Figure 7
● ● ●
modulelab3little(A, B, X, Y, F);
output F;
input A;
input B;
input X;
input Y;
wire A,B,X,Y,F;
assign F = (A&~X&~Y)|(B&~X~Y)|(~A&X&Y)|(B&X&~Y);
endmodule
● ● ●
Figure 9

6. Katrina Little
Experiment #3
Figures 7 depicts the schematic diagram of the function f. Figure 8 shows the pin
numbers for the switches and LED of the system. Figure 9 shows the verilog
interpretation of the function.
TEST PLAN (PROCEDURE):
I. Test the plan using the schematic capture tool.
a. Generate a timing diagram (test bench) to represent all possible bit
combinations.
b. Set both the test bench and the simulation time to 4000 nanoseconds to
allow enough time to cycle through all possible inputs.
c. Simulate behavior model
d. Generate a bit file and download to the BASYS board using the Diligent
Export program.
II. Test the plan using the Verilog language (Repeat steps a-d from part I.)
III. Verify that the circuit design from parts I & II behaves appropriately by checking
when the LED was triggered on the BASYS board. (Which would be the output
F). See the “Results Section.”
I:

7. Katrina Little
Experiment #3
I.a:
II:

8. Katrina Little
Experiment #3
II.a:
II.c:
Figure 7

9. Katrina Little
Experiment #3
CONCLUSIONS (QUESTIONS):
1) Can this multi-function gate be run on an inverter? If yes, explain how.
A: Yes, the multi-function gate can be run on an inverter. The min-term
expansion of F can be written from the karnaugh map in figure 6. The min-terms
of f would be:
F = ∑m(3,5,6,7,8,12,13,14)
Therefore, the min-term expansion of an inverter would be:
F’ = ∑m(0,1,2,4,9,10,11,1)
The Karnaugh map of the function run on an inverter would be seen in figure 10
below.
1 1
1
1 1
1 1
1
0
0 0
00
0
0
0
ab
xy
00
01
11
10
10
00 01 10 11
11
Figure 10

10. Katrina Little
Experiment #3
2) Will the change in the number of inputs or outputs affect the number of operation
select lines? Explain.
A: No, If you add another data input bit you can still use the operation lines X&Y
to AND, OR, NOR, or NAND three bits together as opposed to two.
3) Have you met all the requirements of this lab (Design Specification Plan)
A:Yes.