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1. Code No: A109210503/R09
II B.Tech. Year I Semester Examinations
May/June - 2012
DIGITAL LOGIC DESIGN
( Computer Science and Engineering )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
2 16 8
(b) The solution to the quadratic equation x2
– 11x + 22 = 0 is x = 3 and x = 6. What is the base of the numbers? [7+8]
2. (a) Find the complement of the Boolean function (BC' + A'D) (AB' + CD') and reduce it to a minimum number of
literals and convert the function f(x, y, z) = π(0, 3, 6, 7) to the other canonical form.
(b) Simplify the Boolean function F in sum of products using the don’t care conditions d,
F = y' + x'z'
3. Explain the type of hazard if any in the EXCLUSIVE-OR circuit made by five NAND gates and the EXCLUSIVE OR
circuit made by four NAND gates as shown in figure. [15]
Figure
4. (a) Write the HDL code for 4-bit adder using HALF ADDER, XOR and AND gates as modules.
(b) Explain the implementation of 4-input priority encoder with truth table, K-maps, Boolean functions and sche-
5. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string
of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed.
(i) Obtain state-diagram
(ii) Also obtain state-table
(iii) Find equivalence classes using partition method and design the circuit using D-flip flops. [15]
(b) Write the HDL code for a 4-bit register with parallel load and asynchronous clear. [7+8]
7. (a) Show how to make an 8-to-1 MUX using a PAL. Assume that PAL has 14 outputs and assume that each output
OR gate may have up to four AND terms as input.
(b) Explain how Hamming code is useful for correcting and detecting the errors using an example. [8+7]
8. Explain about all the static and dynamic hazards in sequential circuits. Explain how static hazards are avoided in
asynchronous circuits with an example and neat schematics. [15]
Se t - 1
6. (a) Design an 8-bit counter using eight D-flip-flops.
matic diagrams. [7+8]
d = yz + xy. [8+7]
1. (a) Express the following numbers in decimal: (10110.0101) , (16.5) and (26.24) .

2. Code No: A109210503/R09
II B.Tech I Semester Examinations
May/June - 2012
DIGITAL LOGIC DESIGN
( Computer Science and Engineering )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. Convert the following to Decimal and then to Hexadecimal,
(i) 7448 (ii) 15528
(iii) 110110012 (iv) 111100112
10 10
2. (a) A Boolean switching function is represented by,
f (ABC) = ABC+ ABC+ ABC+ ABC+ ABC+ ABC
(b) Given the Boolean function: F = xy + x'y' +y'z
(i) Implement it with AND, OR, and NOT gates
(ii) Implement it with OR, and NOT gates
3. (a) Find a minimum two-level, multiple-output AND-OR gate circuit to realize these functions,
f1 (a, b, c, d) = m∑ (10, 11, 12, 15) + d∑ (4, 8, 14)
f2 (a, b, c, d) = m∑ (0, 4, 8, 9) + d∑ (1, 10, 12)
3 m∑ d∑
4. (a) Construct a 4 × 16 decoder with two 3 × 8 decoder and also implement a full adder using the 3 × 8 decoder.
(b) Write the HDL code for 4-bit magnitude comparator and also draw a neat schematic. [7+8]
5. (a) Draw the circuit diagram of J-K flip flop with NAND gates with positive edge triggerring and explain its
operation with the help of truth table. How race around condition is eliminated?
(b) Realize D-latch using R-S latch. How is it different from D-flip flop? Draw the circuit using NAND gates and
6. (a) Construct a 4-bit universal shift register with multiplexers and explain the features with a neat schematic.
1 2 3 m∑
(b) Derive a minimal state table for an ASM that acts as a three bit parity generator. For every three bits that are
observed on the input w during three consecutive cycles, the FSM generates the parity bit p = 1 if and only if
8. (a) What is a Hazard in a digital system? What are the various types of Hazards that may be encountered? Briefly
explain.
(b) Find a circuit that has no static hazards and implements the boolean function.
F(A, B, C, D) = ∑
Set - 2
S o l u t i o n s
(0, 2, 6, 7, 8, 10, 12). [7+8]
7. (a) Show the PLA implementation of the function f(x , x , x ) = (1, 2, 4, 7).
the number of 1’s in the three bit sequence is odd. [8+7]
explain. [8+7]
(b) Write the HDL code for an Up-Down binary counter. [8+7]
(iii) Implement it with AND and NOT gates. [7+8]
f (a, b, c, d) = (4, 11, 13, 14, 15) + (5, 9, 12).
(b) Design a combinational circuit that generates 9’s complement of a BCD digit. [8+7]
Find the minimum number of gates needed to realize the above function.
(v) 557 (vi) 739 . [15]

3. Code No: A109210503/R09
II B.Tech I Semester Examinations
May/June - 2012
DIGITAL LOGIC DESIGN
( Computer Science and Engineering )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) Perform the following using BCD arithmetic. Verify the result.
(i) 748410
+366810
10 10
(b) Convert the following,
(i) A616
= ( )10
(ii) 12668
= ( )10
(iii) 101000112
=()10
10 16
(b) A four-variable logic function that is equal to 1 if any three or all four of its variables are 1 is called a majority
3. (a) Find a minimum two level, multiple-output AND-OR gate circuit to realize these functions,
f1
(a, b, c, d) = Σm(3, 4, 6, 9, 11)
f2
(a, b, c, d) = Σm(2, 4, 8, 10, 11, 12)
f3
(b) Explain the operation of a combinational logic simulator that uses four valued logic. [8+7]
4. (a) Write the HDL code for a BCD-to-7-segment code converter using a selected signal assignment.
(b) Implement a three input majority function by using both 4-to-1 and 2-to-1 multiplexers. [8+7]
5. (a) Design a sequential circuit with two D flip-flops A and B, and one input x. When x = 0, the state of the circuit
remains the same. When x = 1, the circuit goes through the state transitions from 00 to 01 to 11 to 10 and back
to 00, and repeats.
(b) Explain the properties of sequential circuits that may be used to reduce the number of gates and flip-flops
during the design. [8+7]
Se t - 3
(iv) 372 = ( ) . [7+8]
(ii) 8254 + 8277 .
2. (a) Explain the basic theorems and properties of boolean algebra.
function. Design a minimum-cost circuit that implements majority function. [7+8]
(a, b, c, d) = Σm(3, 6, 7, 10, 11).

4. 6. (a) Construct a state table and graph for the given circuit in figure and also construct a timing chart for the circuit
for an input sequence x = 10011. Indicate at what times, Z has the correct value and specify the correct output.
(Assume that x changes midway between falling and rising clock edges) initially Q1 = Q2 = 0.
K1 J1
Q1
'
1Q
K2 J2
Q2
'
2Q
X
Clock
X
Clock
X
K1 J1
Q1
'
1Q
K2 J2
Q2
'
2Q
X
Clock
X
Clock
X
Figure
7. (a) Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary
number equal to the square of the input number.
8. (a) Explain the recommended procedural steps for the design of an asynchronous sequential circuit.
(b) Explain about static and dynamic hazards and suggest how hazards can be avoided. [8+7]
(b) Write the HDL code for binary multiplier. [8+7]
(b) Design a code converter circuit that converts Gray code to BCD using PALS. [7+8]

5. Code No: A109210503/R09
II B.Tech. I Semester Examinations
May/June - 2012
DIGITAL LOGIC DESIGN
( Computer Science and Engineering )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) Perform subtraction with the following unsigned decimal numbers by taking 10’s complement of the subtrahend.
Verify the result,
(i) 5250–1321
(ii) 1753–8640
(iii) 20–100
(iv) 1200 – 250. (Unit-I, Topic No. 1.2)
(b) Convert the given gray code number to equivalent binary.
2. (a) Reduce the following function F to a minimum sum-of-products expression,
(A' + C' + D') (A' + B + C') (A + B + D) (A + C + D)
(b) Given two 8-bit strings A = 10101101 and B = 10001110, evaluate result after the following logical operations,
(a) AND
(b) OR
(c) XOR
(d) NOT A
3. (a) Find a minimum two level, multiple-output AND-OR gate circuit to realize these functions,
f1
= ac + ad + db
2
dcadab ++
(b) Implement an 8-to-1 MUX using two 4-to-1 MUXes, two three state buffers and one inverter. [8+7]
5. (a) Design a modulo-6 counter which counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1,.... The counter counts the clock
pulses if its enable input, w, is equal to 1. Use D flip-flops in the circuit.
(b) A sequential circuit has two D flip-flops, A and B, two inputs x and y and one output z. The circuit functions
on the following next-state and output equations,
A(t + 1) = x'y + xA
B(t+1)=x'B+xA
z=B
(i) Draw the logic diagram of the circuit.
(ii) List the state table the sequential circuit.
(iii) Draw the corresponding state diagram. [8+7]
Se t - 4
4. (a) Write the HDL code for an 8-to-3 binary encoder using conditional signal assignment.
f =
(b) Design a 4 bit carry look ahead adder circuit. [8+7]
(e) NOT B. [7+8]
1001001011110010[8+7]

6. 6. (a) Design a 4-bit shift register with parallel load using D flip-flops. There are two control inputs, shift and load.
When shift = 1, the content of the register is shifted by one position. New data is transferred into the register
when load = 1 and shift = 0. If both control inputs are equal to 0, the content of the register does not change.
7. (a) Distinguish between ROM and RAM and also draw the read and write cycle timing diagrams.
1 2 3
8. (a) Distinguish between synchronous and asynchronous sequential circuits and also between stable and unstable
states.
(b) Explain about static and dynamic hazards and also explain atleast one way to remove the hazard. [7+8]
(b) Illustrate the PLA implementation of the function f(x , x , x ) = Σm(1, 2, 4, 7). [7+8]
(b) Write the HDL code for a T flip-flop with an asynchronous clear input. [8+7]