2. Cost Criteria of Logic Circuits
• Parameters used to workout implementation cost for a logic circuit are:
• Literal Cost (L)
• Gate Input Cost (G)
• Gate Input Cost with NOTs (GN)
• Literal is a variable or its complement
• Literal cost is the number of literals that appear in a Boolean expression for the logic
circuit diagram. For example
Ser. # Boolean Function L
1 F = BD + AB‘C + AC‘D‘ 8
2 F = BD + AB’C + AB’D’ + AB’C 11
3 F = (A + B)(A + D)(B + C + D’)(B’ + C’ + D) 10
3. Cost Criteria of Logic Circuits ..
Ser. # Boolean Function L G GN
1 F = BD + AB‘C + AC‘D‘ 8 11 14
2 F = BD + AB’C + AB’D’ + AB’C 11 15 19
3 F = (A + B)(A + D)(B + C + D’)(B’ + C’ + D) 10 14 17
F = A + B C + B’ C’ 5 8 10
F = A B C + A’B’C’ 6 8 11
F = (A + C’)(B’ + C)(A’ + B) 6 9 12
• Gate Input Costs is the number of inputs to the gates in the implementation
corresponding exactly to the given equation or equations.
• Can be found from the equation(s) by finding the sum of:
• all literal appearances
• the number of terms excluding single literal terms, and
• optionally, the number of distinct complemented single literals
• Gate input cost is denoted by G if inverters not counted and GN if inverters
counted.
4. • F = A B C + A’ B’ C’ ; L = 6, G = 8 and GN = 11
• F = (A + C’)(B’ + C)(A’ + B) ; L = 6, G = 9 and GN = 12
• Same function and same literal cost
• But first circuit has better gate input count and better gate input count with
NOTs
• Select it!
Worked Example: Implementation Cost of a Logic Circuit
5. Boolean Function Optimization
• An optimal function can minimize the gate input (or literal) cost of a (a set of) Boolean
equation(s) and thus reducing circuit cost.
• An optimal function has a minimum “gate input cost” is reasonable since it measures
directly number of transistors and wires used in implementing a circuit.
• The simplest expression is not necessarily unique, sometimes 2 or more
expressions satisfy cost criterion applied, in this case either solution is
satisfactory from the cost standpoint
6. • Approach 1: Algebraic Manipulation
• Approach 2: Karnaugh Maps (K-map), QM Method, Petrick’s Method, etc.
• Four common rules are frequently applied for simplifying logic functions
1. complement rule: A + A’ = 1
e.g. A (BC + B’C’) + ABC’ + AB’C = A
2. absorption rule: A + AB = A
e.g. A’B + A’BC (D + E) = AB
3. a common rule: A + A’B = A + B
e.g. AB + A’C + B’C = AB + C
4. an expansion rule: A·1 = A and A + A’ = 1
e.g. AB + A’B’C + BC = A’B + AC
Boolean Function Optimization Approaches
7. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 7
Karnaugh Maps
• Simplification of Boolean expressions using algebraic
manipulation can be time consuming
• Hardware designers often simplify Boolean expressions
using a graphical technique based on the use of a
Karnaugh map (K-map)
• A Karnaugh map is an alternative way for representing
the truth table of a digital logic circuit
0 1
0 m0 m1
1 m2 m3
x
y
Generic Two-Input Karnaugh Maps
0 1
0 x’y’ x’y
1 xy’ xy
x
y
8. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 8
Karnaugh Map Example
• Karnaugh maps show visually all
possible expressions for a particular
truth table
• Consider the following OR Gate
example:
x y z
0 0 0
0 1 1
1 0 1
1 1 1
OR Gate
0 1
0 0 1
1 1 1
x
y
Truth Table
Karnaugh Map
Standard Form: f = x + y
Canonical Form: f = x’y + xy’ + xy
9. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 9
Rules for Gate-Level Minimization Using Karnaugh Maps
1. All 1’s in the Karnaugh Map need to be covered
2. For the simplest Boolean expression, the largest
groupings of 1’s should be picked
• Valid groups of bits are groups of size 1, 2, 4, 8, 16, …, 2n bits
• Valid groups form rectangles
• Rectangles can wrap around the Karnaugh Map
3. Overlapping of rectangles is allowed
4. Use Gray coding for bit groupings (e.g., {00, 01, 11, 10})
10. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 10
Gate-Level Minimization Using Karnaugh Maps
00 01 11 10
00 0 1 0 0
01 1 1 0 0
11 0 1 0 0
10 0 0 0 0
wx
yz
NOTE:
These 4 bits could not be
grouped together as one term
00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
wx
yz
NOTE:
These 4 bits can be
grouped together as one term
f = w’y’z + w’xy’ + xy’z
f = x’z’
11. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 11
Example 3-1 from the Textbook
Map of F(x,y,z) = ∑(2,3,4,5)
F(x, y, z) = x’y + xy’
x
y
z
yz
x
00 01 11 10
0 1 1
1 1 1
12. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 12
Example 3-2 from the Textbook
yz
x
00 01 11 10
0 1
1 1 1 1
Map of F(x,y,z) = ∑(3,4,6,7) = yz + xz’
F(x, y, z) = yz + xz’
x
y
z
13. yz
x
00 01 11 10
0 1 1
1 1 1 1
April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 13
Example 3-3 from the Textbook
Map of F(x,y,z) = ∑(0,2,4,5, 6)
F(x, y, z) = z’ + xy’
x
y
z
14. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 14
Implicants and Prime Implicants
• An implicant is any valid grouping in a Karnaugh Map
• A prime implicant is any valid grouping in a Karnaugh Map that is not a subset of
another valid grouping
• Essential prime implicants are those that cover at least one minterm not covered by
another prime implicant
• Some minterms may be covered by several prime implicants
x
y
z
Implicants:
(m0), (m2), (m4), (m5), (m6),
(m0, m2), (m0, m4), (m4, m5), (m4, m6), (m2, m6),
(m0, m2, m4, m6).
Prime Implicants (PI’s):
(m4, m5), (m0, m2, m4, m6).
Essential Prime Implicants (EPI’s):
(m4, m5), (m0, m2, m4, m6).
yz
x
00 01 11 10
0 1 1
1 1 1 1
15. Map of F(x,y,z) = ∑(0,2,4,5, 6)
Implicants:
(m0), (m2), (m4), (m5), (m6),
(m0, m2), (m0, m4), (m4, m5), (m4, m6), (m2, m6),
(m0, m2, m4, m6).
Prime Implicants (PI’s):
(m4, m5), (m0, m2, m4, m6).
Essential Prime Implicants (EPI’s):
(m4, m5), (m0, m2, m4, m6).
x
y
z
yz
x
00 01 11 10
0 1 1
1 1 1 1
Minimized function is:
1. Sum all EPI’s, and
2. PI’s with missing minterms from the function
Minimized Function using EPIs and PIs
F(x,y,z) = ∑(0,2,4,5, 6) = m0 + m2 + m4 + m5 + m6
= (m0 + m2 + m4 + m6 ) + (m4 + m5)
= z’ + xy’ ∴ (m0 + m2 + m4 + m6 ) = z’ & (m4 + m5) = xy’
=
16. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 16
Number of Literals in a Term
Number of
Adjacent
Squares
Number of Literals in a
Term in an n-variable
Map
K 2k n = 2 n = 3 n = 4 n = 5
0 1 2 3 4 5
1 2 1 2 3 4
2 4 0 1 2 3
3 8 0 1 2
4 16 0 1
5 32 0
17. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 17
Product of Sums Simplification
• Karnaugh maps can be used to expression a function f in
a sum of products form or a product of sums form
• For a sum of products, the function f is equal to the sum
of all minterms that produce a 1.
• For a product of sums, the function f’ is equal to the
sum of all minterms that produce a 0.
• Using DeMorgan’s Theorem, it is possible to convert a sum of products expression
for f’ into a product of sums expression for f
18. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 18
Sum of Products Using Karnaugh Maps
00 01 11 10
00 0 1 0 0
01 1 1 0 0
11 0 1 0 0
10 0 0 0 0
wx
yz
NOTE:
Recall this example.
00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
wx
yz
f = w’y’z + w’xy’ + xy’z
f = x’z’
NOTE:
Recall this example.
19. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 19
Product of Sums Using Karnaugh Maps
00 01 11 10
00 0 1 0 0
01 1 1 0 0
11 0 1 0 0
10 0 0 0 0
wx
yz
00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
wx
yz
f’ = y + wx’ + x’z’ + wz’
f = (y’)(w’ + x)(x + z)(w’ + z)
f’ = x + z
f = x’z’
NOTE:
Both the function f’ and f
are shown for clarity. For
a product of sums
representation, the 0’s are
circled to find f’. Using
DeMorgan’s Theorem, f is
then determined.
20. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 20
Using Algebraic Manipulation…
• It is possible to show that the sum of products and
product of sums expressions are equivalent.
• In other words, the following is true:
(y’)(w’ + x)(x + z)(w’ + z)
= w’y’z + w’xy’ + xy’z
• Proof:
(y’)(w’ + x)(x + z)(w’ + z)
= (w’y’ + xy’)(w’x + w’z + xz + z)
= w’xy’ + w’xy’ + w’y’z + w’xy’z + w’xy’z + xy’z + w’y’z + xy’z
= w’xy’ + w’y’z + w’xy’z + xy’z
= w’y’z + w’xy’ + xy’z
21. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 21
Five-Variable Karnaugh Maps
• Rather than write large Karnaugh maps in one large matrix,
it is possible to split Karnaugh maps into two or more tables
• For five-variable Karnaugh maps, it often makes sense to
split the map into two tables as shown below:
22. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 22
Example 3-7 from the Textbook
23. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 23
Comments on Splitting Karnaugh Maps
• You must be very careful if you split a Karnaugh map
• Example 3-7 illustrates an important simplification to
note:
• BD’E appears in the Karnaugh Map for both A = 0 and A = 1
F = A’B’E’ + ACE + A’BD’E + ABD’E
F = A’B’E’ + ACE + BD’E
• It is very easy to miss this simplification!
24. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 24
Don’t Care Conditions
• Sometimes, the output of a function really doesn’t
matter
• Example of a Don’t Care Condition:
Consider a digital circuit that outputs two signals. The
first signal indicates whether the digital circuit is
enabled or not. The second signal represents the
output of the digital circuit when enabled.
In this situation, the second signal is irrelevant if the
first signal indicates that the digital circuit is disabled. In
this case, the second signal and the output signal are in
don’t care conditions.
25. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 25
Don’t Care Conditions
• In a truth table, don’t care conditions are represented by an
X
• Two possible truth tables for the example of a don’t care
condition discussed previously are shown below:
x y f
0 X X
1 0 0
1 1 1
x y f
0 0 X
0 1 X
1 0 0
1 1 1
OR
NOTE:
Don’t care conditions are sometimes
indicated by the use of a ‘-’.
26. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 26
Don’t Care Conditions
• In a Karnaugh map, don’t care conditions are represented
by the letter X
• The Karnaugh map for the example of a don’t care condition
discussed previously is shown below:
0 1
0 X X
1 0 1
x
y
• This Karnaugh map can be represented by several functions:
f = y Transfer
f = (x y)’ XNOR
f = xy AND
27. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 27
Importance of Don’t Care Conditions
• Don’t care conditions introduce design flexibility
• When writing a truth table (or a Karnaugh map), always
use an X for an output if a don’t care condition exists
• A don’t care condition can be treated as either a 0 or a
1 during simplification
28. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 28
Evaluating Don’t Care Conditions
• Don’t care conditions cannot be simultaneously treated
as a 0 and a 1
• In other words, if one term requires the value to be a 1, then it is treated as a 1 for
ALL terms
• All don’t care conditions should be considered
independently
• Some may be treated as a 1 while others may be treated as a 0
• For large numbers of don’t care conditions, the number
of prime implicants to consider can be quite large
• EDA (Electronic Design Automation) tools such as Xilinx
ISE can evaluate don’t care conditions to determine the
simplest implementation possible
29. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 29
Example 3-9 from the Textbook
30. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 30
Example 3-9 as a Product of Sums
f’ = z’ + wy’ Complement of f
f = z(w’ + y) Product of Sums
f = w’z + yz Sum of Products
31. Quine-McCluskey (QM) Method
• Quine-McCluskey method is a systematic simplification procedure that
can be applied by computer.
• The method reduces the minterm expansion of a function to obtain a
minimum sum of products.
• The QM Algorithm is based on two steps:
1. Eliminate as many literals as possible by applying
XY+XY' = X. Resulting terms are prime implicants Pis.
2. Use a chart of prime implicant to select a minimum set of
prime implicants.
32. AB’CD’ + AB’CD = AB’C
10 10 + 10 11 = 10 1-
(dash indicates missing variable)
Function must be given in sum of minterms form.
Minterms are combined using XY+XY' = X
To reduce the number of comparisons, binary minterms are sorted by
number of 1's in each term.
Compare terms that differ in only one bit position. Only terms with
dashes in the same position are considered.
QM Method Step 1 - Determination of PIs
X Y X Y’ X
33. QM Method - Determination of PIs - Example
All of the prime implicants have been found. i.e.
f(a,b,c,d) = a'b'd' + a'cd' + a'bc + bcd' + b'c'
However, f(a,b,c,d) has not yet been minimized.
Remember, the minimum function includes some but not necessarily all of the prime
implicants!
PI’s for f(a,b,c,d) = ∑(0,1,2,6,8,9,7,14)
idx Bidx Iteration 1 Iteration 2
group 0
0 0000 (0,1)
(0,2)
(0,8)
000-
00-0
-000
(0,1,8,9)
(0,8,1,9)
-00-
group 1
1 0001 (1,9)
(2,6)
(8,9)
-001
0-10
100-
2 0010
8 1000
group 2
6 0110 (6,7)
(6,14)
011-
-110
9 1001
group 3
7 0111
14 1110
34. QM Method Step 2 - PIs Chart
• Step 2 of QM Method is to select minimum set of prime implicants.
• For the purpose, PI Chart is constructed as follows:
Minterms are placed across top
Prime implicants listed on side
X placed at intersections if prime implicant covers minterm
Prime Implicant Chart
Prime Implicant Expression 0 1 2 6 7 8 9 14
(0,2) a'b'd' x x
(2,6) a'cd' x x
(6,7)* a'bc x x
(6,14)* bcd' x x
(0,1,8,9)* b'c' x x x x
• If a minterm is covered only by one prime implicant, that prime implicant is
called an ESSENTIAL PRIME IMPLICANT. E.g. EPIs are *ed in the table.
• Once all of the essential prime implicants have been identified, select a
minimum set of prime implicants to cover the remaining minterms.
• Result is f(a,b,c,d) = ∑(0,1,2,6,8,9,7,14) = ∑(0,1,8,9) + ∑(2,6) + ∑ (6,7) + ∑(6,14)
• = b'c' + a'cd' + a'bc + bcd'
K Map
abcd 00 01 11 10
00 1 1 1
01 1 1
11 1
10 1 1
f(a,b,c,d)= b'c' + a'cd' + a'bc + bcd'
36. abcd 00 01 11 10
00 x x 1
01 x 1 1
11 1 1 1
10 1
f = bd’ + a’d’ +a’bc’ +acd
PI’s Chart (Do not include don't cares for prime implicant chart)
PI Expression 2 5 6 11 12 14 15
(2,3) a'b'c x
(4,5)* a'bc' x
(3,11) b'cd x
(11,15) acd x x
(14,15) abc x x
(0,2,4,6) a'd' x x
(4,6,12,14)* bd' x x x
QM Method Example
• The minimized f(a,b,c,d) must include all the minterms except don’t cares
minterms i.e. 2,5,6,11,12,14&15.
f(a,b,c,d) = ∑m(2,5,6,11,12,14,15) = ∑m(4, 6,12,14) + ∑m(4,5) + any PI’s covering missing
minterms 2,11 & 15
f(a,b,c,d) = ∑m(2,5,6,11,12,14,15) = ∑m(4, 6,12,14) + ∑m(4,5) + ∑m(0, 2,4,6) + ∑m(11,15)
= bd’+a’d’ + a’bc’+ acd
abcd 00 01 11 10
00 x x 1
01 x 1 1
11 1 1 1
10 1
f = bd’ + a’d’ +a’bc’ + b’cd +abc
38. abcd 00 01 11 10
00 x x 1
01 x 1 1
11 1 1 1
10 1
f = bd’ + a’d’ +a’bc’ +acd
PI Chart for F(A,B,C,D)=∑m(2,3,7,9,11,13)+∑d(1,10,15)
PI Expression 2 3 7 9 11 13
(1,3,9,11) b'd x x x
(2,3,10,11)* b'c x x x
(3,7,11,15)* cd x x x
(9,11,13,15)* ad x x x
QM Method Example-2
• The minimized f(a,b,c,d) must include all the minterms except
don’t cares minterms i.e. 2,3,7,9,11 &13.
f(a,b,c,d) = ∑m(2,3,7,9,11 ,13)
= ∑m(2, 3,10,11) + ∑m(3,7,11,15) + ∑m(9,11,13,15) +
any PI’s covering missing minterms 2,11 & 15
f(a,b,c,d) = ∑m(2,3,7,9,11 ,13)
= ∑m(2, 3,10,11) + ∑m(3,7,11,15) + ∑m(9,11,13,15)
= b’c+ ad + cd
abcd 00 01 11 10
00 x x 1
01 x 1 1
11 1 1 1
10 1
f = bd’ + a’d’ +a’bc’ + b’cd +abc
39. • Petrick's method or the branch-and-bound method is a technique for
determining all minimum sum-of-products solutions from a prime
implicant chart.
1. Reduce the prime implicant chart by eliminating the essential prime implicant rows and the
corresponding columns.
2. Label the rows of the reduced prime implicant chart P1, P2, P3, P4, … etc.
3. Form a logical function P which is true when all the columns are covered. P consists of a
product of sums where each sum term has the form (Pi0 + Pi1 + … + PiN), where each Pij
represents a row covering column i.
4. Reduce P to a minimum sum of products by multiplying out and applying X + XY = X.
5. Each term in the result represents a solution, that is, a set of rows which covers all of the
minterms in the table. To determine the minimum solutions, first find those terms which
contain a minimum number of prime implicants.
6. Next, for each of the terms found in step five, count the number of literals in each prime
implicant and find the total number of literals.
7. Choose the term or terms composed of the minimum total number of literals, and write out
the corresponding sums of prime implicants.
Petrik’s Method
40. • Petrick's Method finds all minimum sum-of-products solutions for a given function
Petrik’s Method Example
Petrick’s Method Example
PI’s for f(a,b,c,d) = ∑m(2,5,6,11,12,14,15)+∑d(0,3,4)
idx Bidx Iteration 1 Iteration 2
group 0
0 0000 (0,2)
(0,4)
00-0
0-00
(0,2,4,6)
(0,4,2,6)
0--0
0--0
group 1
2
4
0010
0100
(2,3)
(2,6)
(4,5)
(4,6)
(4,12)
001-
0-10
010-
01-0
-100
(4,6,12,14)
(4,12,6,14)
-1-0
-1-0
group 2
3
5
6
12
0011
0101
0110
1100
(3,11)
(6,14)
(12,14)
-011
-110
11-0
group 3
11
14
1011
1110
(11,15)
(14,15)
1-11
111-
group 4 15 1111
41. PI’s Chart (Do not include don't cares for prime implicant chart)
Assigned Name PI Expression 2 5 6 11 12 14 15
K (2,3) a'b'c x
V (4,5)* a'bc' x
L (3,11) b'cd x
M (11,15) acd x x
N (14,15) abc x x
P (0,2,4,6) a'd' x x
W (4,6,12,14)* bd' x x x
K+P L+M M+N
To reduce the equation, Petrick's Method uses the identities (X + Y)(X + Z) = X + YZ and X + XY = X
F = ∑EPI’s + A term from Q
Q = (K+P)(L+M)(M+N)
= (K+P)(M+LN)
= KM+KLN+MP+LNP
f(a,b,c,d) = a’bc’+bd’+
a’b’c + acd KM
a’b’c + b’cd + abc KLN
acd + a’d’ MP
b’cd + abc + a’d’ LNP
Petrik’s Method Example
42. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 42
Comments on Boolean Functions
• Any Boolean function can be expressed using a
combination of AND, OR, and NOT gates.
• The reasoning for this is the following:
1. Any Boolean function can be expressed using a truth table
2. Any truth table can be expressed as a sum of products
3. Any sum of products can be converted to a combination of AND, OR, and NOT
gates
• Both NAND gates and NOR gates are capable of
implementing AND, OR, and NOT gates
• Hence, NAND gates and NOR gates implement a
functionally complete set of gates.
43. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 43
NAND Implementations of AND, OR, and NOT Gates
NOT Gate
AND Gate
OR Gate
x
x
x
y
y
f
f
f
f = x’
f = ((xy)’)’ = xy
f = (x’y’)’ = x + y
44. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 44
NOR Implementations of AND, OR, and NOT Gates
x
x
y
x
y
f
f
f
NOT Gate
AND Gate
OR Gate
f = x’
f = (x’ + y’)’ = xy
f = ((x + y)’)’ = x + y
45. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 45
Interesting Properties of XOR Gates
• XOR gates have the following interesting properties:
x 0 = x
x 1 = x’
x x = 0
x x’ = 1
x y’ = x’ y = (x y)’
x y = y x
x y z = (x y) z = x (y z)
46. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 46
Uses of XOR Gates
• Arithmetic operations
• Error-detection and correction (parity generation)
47. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 47
Two-Input XOR and XNOR Gates
NOTE:
The course material on XOR and XNOR gates has been
adapted from the course notes for ECE 223 provided by
Dr. Andrew Kennings
48. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 48
Two-Input XOR Implementation Using AND, OR, and NOT Gates
x
y
x y
49. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 49
Two-Input XOR Implementation Using NAND Gates
x
y
x y
50. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 50
Four-Input XOR and XNOR Gates
52. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 52
Example of XOR Extraction
0
1
01
00
0
1
00
01
x1x2
x3x4
0
1
1
0
11 10
11
10
0 0
1 1
0 0
1 1
• Given a Boolean function f, is it possible to simplify this
complex sum of products function using XOR and XNOR
gates?
• Consider the following Karnaugh Map:
NOTE:
This Boolean function uses six
terms in sum of products form.
53. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 53
Example of XOR Extraction
0
1
01
00
0
1
00
01
x1x2
x3x4
0
1
1
0
11 10
11
10
0 0
1 1
0 0
1 1
XNOR XOR
54. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 54
Example of XNOR Extraction
Simplifying…
Arguably, this simplified expression using two XOR gates will
require fewer total gates to implement the function
QUESTION:
How do you find the optimal solution?
55. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 55
Optimal Gate Implementations
• If nothing else, the previous example should make it
clear that optimal gate implementations are not easy to
determine
• Many alternative implementations exist
• Direct evaluation of every alternative is intractable for most practical applications
• The problem of finding an optimal solution becomes
more complex if there are many outputs to be
considered
• May be possible to reuse intermediate nodes to reduce the number of gates
required
• Must consider all outputs simultaneously
• To further complicate the problem, fewer gates and
literals does not necessarily lead to a “better” design
56. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 56
Synthesis and Logic Optimizations
• Synthesis tools use heuristics to obtain “near-optimal”
solutions
• Fast logic synthesis is an active area of research
• Fast logic synthesis becomes more challenging every year given the trend of digital
circuits growing in complexity at an exponential rate
• Fast heuristic solvers are essential
57. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 57
Example of Reuse of Intermediate Nodes
• Consider the following functions f1 and f2:
f1 = x + y
f2 = xz + yz
• A simple solution is the following:
x
y
x
y
z f2
f1
58. April 13, 2023 Lecture Notes - EE 222: Digital Logic Design 58
Example of Reuse of Intermediate Nodes
• Consider the following functions f1 and f2:
f1 = x + y
f2 = xz + yz = (x + y)z
• A more advanced solution is the following:
x
y
z
f2
f1