Digital systems: Design of a Burglar Alarm using Simple Combinational Logic. FPGA design verified on BASYS experimenter board utilizing Verilog programming language in Xilinx design suite.

1. Katrina Little
Experiment #2:
Simple Combinational Logic

2. Katrina Little
Experiment #2
Page number 2
OBJECTIVES:
 Execution of a simple combinational logic circuit to further get
acquainted with Xilinx’s ISE procedures.
 Learn how to implement a design from nothing but a simple idea for a burglar
system alarm.
EQUIPMENT LIST:
 FPGA BASYS1 board
 Xilinx ISE program
 Flash Drive
 BIT file
BLOCK DIAGRAM:
DESIGN SPECIFICATION PLAN:
The idea is to design a burglar alarm system. The alarm will need to sound if and only if
the power of the alarm system is turned ON, and either a window or door has been
opened. Also, the alarm should sound if a door and window are both open. To easily
recognize the possible combinations required for the alarm to sound, please refer to
Figure (2).
Burglar Alarm
Controller
Power(P)
Window (W)
Door (D)
Alarm
(A)
FIGURE (1)

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Experiment #2
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Figure (2)
DESIGN METHODOLOGY:
From the design specification plan, techniques
to create the system can be drawn by careful
reasoning.
Since the design specification says the power
has to be on and either a window or door is open,
appropriate gates can easily be established from
the context of the plan. The truth table in FIG(3)
gives a visual representation of what makes
these conditions true.
POWER WINDOW DOOR
ON CLOSED OPEN
ON OPEN CLOSED
ON OPEN OPEN
P W D A
1 0 1 1
1 1 0 1
1 1 1 1
INV ‘
AND +
OR *
Figure(3)
Truth table that states the conditions to
be met for the burglar alarm to sound. P,
W, D, & A stand for power, window,
door, and Alarm respectively. 1 signifies
true. Which means open for W or D, on
for P , and alarm triggered for A. 0
means closed for W or D. Note: this truth
table is incomplete. Since there are 3 bits
eight total combinations will need to be
tested.
Since the windows and doors can be one or zero we will need to use
inverter gates for those two aspects only. To get every status
combination of power, windows, and doors we will need three (3 bit) and
gates (two of which the inverters will feed into). We will need one and
gate with a window open and power on, one with a door open and power
on, and lastly, one with the window/door open and power on. Finally, to
get the final output (the alarm) to trigger, we will need one or gate that
the three and gates will feed into. See Figure (5a)
Figure (4):
Operations of each gate

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Experiment #2
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Interpreting the one’s from the truth table in Figure 3 you can write the alarm as a
function of P, D, and W using “Sum of Products,” (SOP) as shown.
A(PDW) = PW’D + PWD’ + PDW
DETAILED SCHEMATIC DIAGRAM:
INPUT/OUTPUT SWITCH PIN # LED #
P SW0 36
D SW1 38
W SW2 29
A 15 0
P
P
P
D
D
W
W
W
A
D
Figure (5a)
Figure (5a):
(left) displays
the design
schematic for
the alarm
system. Figure
5b: (bottom left)
is the Verilog
language
interpretation.
Figure 6 (below)
is the legend for
the switch, pin,
and led
configuration
for the input s
and output of
the function on
the BASYS(1)
board.
Figure (6)
● ● ●
module veriloglittlelab2(A, P, D, W);
output A;
input P;
input D;
input W;
assign A =
((P&D&(~W))|(P&(~D)&W)|(P&D&W));
endmodule
● ● ●
Figure(5b)

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Experiment #2
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TEST PLAN (PROCEDURE):
The test plan was broken into three parts essentially:
I. Test the plan using the schematic capture tool.
a. Generate a timing diagram (test bench) to represent all possible bit
combinations.
b. Set both the test bench and the simulation time to 2000 nanoseconds to
allow enough time to cycle through all possible inputs.
c. Simulate behavior model
d. Generate a bit file and download to the BASYS board using the Diligent
Export program.
II. Test the plan using the Verilog language (Repeat steps a-d from part I.)
III. Verify that the circuit design from parts I & II behave appropriately by checking
when the LED was triggered on the BASYS board. (Which would be the output
A). Refer to “Results Section.”
I:

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Experiment #2
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I.a:
I.c:

7. Katrina Little
Experiment #2
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II: (see Fig 5b above)
II.a:
II.c:

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Experiment #2
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RESULTS:
CONCLUSIONS (QUESTIONS):
1) Can the logic be simplified in any way?
A: Yes, refer to figure (8) for proof.
PDW’ +PD’W +PDW
 factor out P: P(DW’ +D’W +WD)
 by using simplification theorem #9 XY +XY’ = X on the last two terms
leaves:
 P(DW’ +W)
 by simplification theorem #11D XY’ + Y =X +Y leaves:
 P(D + W) = PD +PW
 therefore, A = PD +PW
PDW D’ W’ PDW’ PD’W PDW A = PDW’ + PD’W
+ PDW
000 1 1 0 0 0 0
001 1 0 0 0 0 0
010 0 1 0 0 0 0
011 0 0 0 0 0 0
100 1 1 0 0 0 0
101 1 0 0 1 0 1
110 0 1 1 0 0 1
111 0 0 0 0 1 1
Figure (7)
Figure 8
D
P
W
A
Figure 9
Figure (8)

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Experiment #2
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2) How would the controller logic be simplified if the power is always on?
A: If you refer to figure 7, the power is always on ONLY in the last four columns
(for this design plan). Since there are four rows, included in the results with the
power on (three of which have 1’s and one of which has a zero), it would be
easier to write the function for the alarm using the one 0 using SOP.
A(PDW) = (P’ + D +W)
Therefore, the logic would be simplified to one (3bit) OR gate and an inverter for
the power. Refer to figure 9.
3) Have you met all requirements of this lab (Design Specification plan)?
A: Yes.
4) How should your design be tested?
A: The design was tested on the BASYS(1) board after it was programmed
successfully with the generated BIT file for both parts I & II of the test plan. The
results of the designs were found by moving the switches on the BASYS(1)
board to every different combinational bit of P, D, and W as seen in figure 7
above. The results for BOTH parts agreed with the design specification plan. The
alarm sounds ONLY when the power is set to on AND, either a window or door is
open, or both the window and door are open. These three representations are
shown at PDW = 101, 110, and 111 on the truth table. You can easily see that
the alarm is set to 1 (triggered) at these three points on the truth table.
5) The function is represented by the ORing in terms associated with the 1’s in the
truth table. Can an expression for A be found which is derived by the ANDing of
terms associated with the 0’s in the truth table?
A:
Yes it can. To write an expression using the zeroes would mean using “product
of sums” (POS) instead of “sum of products.” Using this method would be more
complicated because there are more zeroes than ones on the truth table.

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Typically, the general consensus is to use whichever method has the least
numbers. (I.e. use POS if there are less zeroes or SOP if there are less ones.)
Therefore, using POS, the expression for the alarm becomes: NOTE: when using
POS opposed to SOP you want your equation to equal zero.
A(PWS) = (P+D+W)(P+D+W’)(P+D’+W)(P+D’+W’)(P’+D+W)
It can easily be seen that this expression is much more complicated than the one
that was used by “ORing” the terms together.
6) Write the Boolean expression describing a burglar alarm, which also sounds
when a sensor has been crossed.
A: The same will be true for the power here. The power will have to be ON in
ALL cases.
Therefore, adding a sensor component, the possible situations that will trigger
the alarm are as follows:
Power Door Window Sensor Alarm
ON CLOSED CLOSED OPEN ON
ON CLOSED OPEN CLOSED ON
ON CLOSED OPEN OPEN ON
ON OPEN CLOSED CLOSED ON
ON OPEN CLOSED OPEN ON
ON OPEN OPEN CLOSED ON
PLEASE NOTE: NOW THAT THERE ARE NOW 4 COMPONENTS ( BITS).
THEREFORE, TO TEST THIS CONFIGURATION OF THE ALARM SYSTEM,
THE TRUTH TABLE WILL NEED TO HAVE FOUR BITS.
Figure 10: Modified logical thinking of burglar alarm system with added sensor

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Experiment #2
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P D W S A
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Writing the Boolean Expression using the ones from the table gives:
A(P,D,W,S) = PD’W’S +PD’WS’ + PD’WS + PDW’S’ +PDW’S +PDWS’ +PDWS
 Factoring out P gives:
 P(D’W’S + D’WS’ + D’WS + DW’S’ + DW’S + DWS’ + DWS)
 Term 1 and term 7 will cancel out.
 Term 2 and term 5 will cancel out.
 Term 3 and term 4 will cancel out.
 Which simply leaves : DWS
Therefore, the Boolean expression for the burglar alarm WITH the added sensor
is:
A(P,D,W,S) = PDWS.
Adding the extra component (sensor) actually simplifies the logic of the system.
Figure 11: the corresponding partial
truth table (showing only possible
ways to make alarm sound)