This document describes the design of a Wallace tree multiplier using Verilog. It discusses different types of multipliers such as array, serial/parallel, and Booth multipliers. It provides details on the Wallace tree multiplier design including its block diagram, partitioning of partial products, number of levels, submodules like AND gates and full adders, and comparison of its power consumption and results. The dumping process in an FPGA kit is also covered along with the advantage of small delay and disadvantage of complex layout for the Wallace tree multiplier.

1. DESIGN OF WALLACE TREE
MULTIPLIER USING VERILOG
UNDER the guidance of :
K.Thrisandhya
Assistant professor
B. HARI KRISHNA (12841A04J6)
K.VAMSHI KRISHNA (12841A04M7)
N.V.CHARAN TEJ (12841A04H9)

2. Binary multiplication

3. Different types of multipliers
• Binary multiplier
• Array multiplier
• Serial/parallel multiplier
• Wallace tree multiplier
• Booth multiplier

4. Array multiplier

5. Advantages and disadvantages
Advantages
• Minimum complexity
• Easily schedule
• Easily pipelined
• Regular shape
Disadvantages
• High power consumption
• Large area
• Delay

6. BLOCK DIAGRAM

7. Partition of the partial products

8. NUMBER OF LEVELS IN WALLACE TREE

9. Wallace tree multiplier

10. SUB MODULES
• AND gate
• Half adder
• Full adder

11. And gate

12. Half adder

13. Full adder

14. COMPARISION TABLE

15. POWERCONSUMPTION

16. RESULTS OF WALLACE TREE
MULTIPLIER

20. DUMPING PROCESS IN FPGA

21. Dumping process in FPGA kit

22. Dumping process in FPGA kit

23. OUTPUT OF FPGA
OUTPUT

24. Advantage and disadvantage
• Advantage of the Wallace tree is small delay.
• logic levels required to perform the summation can be
reduced.
Disadvantage :-
• It is complex to layout.
• It has irregular wires.

25. CONCLUSION
• Modified Booth and Wallace Tree are the best techniques for high
speed multiplication.
• Wallace Tree has the best performance, but it is hard to
implement.