1. Resume Soumya V
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Soumya V
E-mail: v.soumyaa@gmail.com
Cell: +91 9538526950
Objectives: To be an efficient VLSI designer in a firm that provides a professional and
challenging environment to explore and enhance my technical and interpersonal skills thus
contributing towards company objective
Experience Summary
Current Profile: ASIC Design Engineer at Open Silicon, Bangalore [From 1st
July 2015]
Domain: Physical design for ASICs
Previous Profile: Intern at Nxp Semiconductors India PVT LTD [Oct 2014 – Jun 2015]
Employed by Robert Bosch Engineering and Business Solutions Limited (100%
owned subsidiary of Robert Bosch GmbH)
Worked as:
Senior software Engineer - Oct 2012 – Jul 2013
Associate software Engineer – Oct 2010 – Sept 2012
Educational Qualification:
Qualification Year
obtained
School/College Class/Grade and
%
Remarks
MTech (VLSI
Designing)
2013-2015 Vellore Institute of
Technology, Chennai
CGPA 9.08 Distinction
BE (Electronics &
Communication)
2006-2010 Jawaharlal National
College of Engineering,
Shimoga
80.14% First Class with
Distinction
(FCD)
PUC 2004-2006 Deshiya Vidhya Samste
Composite College,
Shimoga
89.83 Distinction(PCM
95%)
SSLC 2001-2004 Mary Immaculate Girls’
High School, Shimoga
96 Distinction

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Technical Skills:
Operating System UNIX, Fedora, Windows7 Professional, Windows XP
Languages Verilog, Perl, TCL, Python, C
Defect Management Tools JIRA, MMS
Tools Cadence-Virtuoso RC Encounter NcSimulator , Xilinx, Modelsim,
Liberate, Vector CANoe
Soft skills:
 Quick Learning Ability: During the two and half year tenure of work experience have worked on
various modules of infotainment system. As an MTech intern have worked in standard cell library
development and currently have adapted well as Physical design engineer.
 Team Worker: Have worked in a team of 22 members which was located in different locations like
Bangalore, Coimbatore, Leonberg and Hildesheim and have coordinated the work activities from
customer location.
 Easy adaptability: Have worked in various work environments both onsite and offshore which has
given an exposure to global work culture.
Experience Details:
Project Title PHYSICAL DESIGN for JVC video chip
Period Jan,2016 till date
Responsibilities  Block level Floorplan
 Block level CTS
 Block level PNR
 Block level Time Closure
 Block level DRC and LVS
 Block level LEC clearance
Tools Cadence Encounter, Mentor graphics Caliber, Cadence Conformal
Technologies GF55
Project Title LOGIC LIBRARIES DESIGN
Period October,2014 – June,2015
Responsibilities  Layout optimisation of standard cells
 Characterisation of standard cell libraries
 Generating different views for standard cells like Verilog
Voltagestorm, Celtic etc using company specific tool flow
 Running sign off checks
Tools Liberate, Cadence Virtuoso, Cadence Conformal
Technologies 90nm, 40nm and 140nm

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Project Title PAG – ICM
Period October,2010 – July,2013
Client Premium automotive group, Volvo
Variants Europe, US, China and Japan
Responsibilities  Analyzing the requirements with respect to HMI and Network
communication
 Creating Manual test cases and Automated test cases
 Setting up test environment
 System testing of individual modules in ICM (Media Player, RSE,
Phone, Navigation)
 Managing and reporting bugs
 Support to the development team by providing CAN, MOST, TTFIS
traces
Project PAG-ICM is an acronym for Premier Automotive Group Infotainment Control
Module which acts as Display Interface to the end user to reach and control
various functionalities/facilities available in a modern car.
The project is a typical example of a distributed system comprising of various
infotainment nodes as well as ECU’s, which communicate with each other
using MOST, CAN and LIN protocols.
Tools Vector CANoe, SiTemppo, Doors, Docushare, JIRA, MMS
Technologies Basic C, CAPL, CAN, MOST, LIN
Onsite Experience:
Project Title PAG – ICM
Period August,2011 – June,2012
Location Stuttgart, Germany
Responsibilities  In car tests of ICM with Volvo S60, XC70, V90
 Regression test execution
 Manual test of Europe specific features like Telematics and DVBTV
 Client Interaction and supporting the offshore team with tests to be
performed in Car
 Support to the development team by providing traces from real car for
analyzing and fixing the issues
Academic Projects:
Project Title Design of a CORDIC processor
Period October,2014 – May,2015
Project Design of a processor with hardwired instructions for sine, cosine, sinh, cosh,
multiplication and division. COordinate Rotation Digital Computer (CORDIC)
algorithm is used for efficient hardware implementation of these functions.

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Processor is designed with Parallel and Pipelined CORDIC architectures.
Performance parameters are measured and compared. The processor is also
provided with instructions for generating sine, cosine, sinh, cosh and
exponential waves, thus can be used a waveform generator. The Parallel
processor operates at 24.23MHz and Pipelined processor operates at
254.45MHz.
Tools Cadence – NC simulator, Encounter, Voltus and Xilinx
Publication Indian Journal of Science and Technology, Vol 8(19), IPL0129, August
2015
Project Title Design of a unified field reconfigurable cryptographic processor
Period January,2014 – April,2014
Project Implementing cryptographic algorithms using general purpose processors is
flexible but results in low throughput and high power consumption. ASIC
implementation of such algorithms results in high throughput but not flexible.
Thus to bridge the gap between these two implementations application specific
cryptographic processors are designed. The processor has a reconfigurable
data-path which can perform either GF(p) or GF(2m) operations on prime
numbers and irreducible polynomials. With the proposed instruction set the
users are capable of programming public key cryptosystems like Rivest–
Shamir–Adleman (RSA) or elliptic curve cryptosystems and private key
cryptosystem AES.
Tools Cadence – NC launch, Encounter and Xilinx
Project Title Design of an AES (Advanced Encryption Standard ) S-Box using an
adiabatic logic style called DCPAL
Period July,2013 – November,2013
Project Advanced Encryption Standard (AES) algorithm is one of the widely used
encryption algorithm. SubByte substitution phase of this algorithm is the most
performance demanding stage in implementation of AES algorithm. Thus
efficient implementation of AES S-Box would enhance the efficiency of the
algorithm. DCPAL (Differential Cascode Adiabatic Logic) is an energy
efficient logic style which has proved to be more resistant to Differential
Power Analysis attacks thus enhancing the security promised by AES
algorithm.
Tools Cadence Virtuoso
Project Title Human Motion Tracer using mobile communication
Period March,2010 – June,2010
Project This project involved designing a simple robot which was controlled using
GSM signals via a mobile phone implanted on the robot. Since GSM signals
are used for controlling the robot the range of the robot is very high. A Passive
Infrared Sensor (PIR) is used to detect the motion of living things around.
Thus this robot can be used as a rescue robot in places which are not accessible
for human beings.

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Tools Keil micro vision
Other Accomplishments:
 ISTQB(International Software Testing Qualification Board) foundation level certified tester
 Qualified in German language A1 level
Personal Details:
Name Soumya V
Date of Birth 28th August 1988
Sex Female
Marital Status Single
Permanent Address Kalasourabha, 7th
cross, ‘A’ Block, Sharavathinagar,
Shimoga-577201
Contact Number +919538526950