The document discusses Direct Memory Access (DMA) and bus masters in the Industry Standard Architecture (ISA). It describes the DMA signals in ISA, the different modes of DMA transfers, DMA channel assignments, and how DMA priority logic works. It also discusses the addressing capabilities of DMA controllers and how ISA bus masters request and use the bus.

1. ISA DMA & Bus Masters By Nishant H. Shah Roll No : 0412096 Batch : B4

2. What is DMA ? ISA DMA Signals Modes of Dma Tranfers Dmac Priority Logic Dmac Adressing capabilty ISA Bus Master

3. ISA Bus Master All The Channels of DMA is Programmed for Cascaded Mode Bus Master is Attached To Master DMAC

4. ISA DMA Signal Lines DRQ [3:0] - DMA Request DRQ [7 :0] - DMA Request DAK# [3:0] - DMA Acknowledge DAK# [7:5] - DMA Acknowledge TC - Transfer Complete Master16# - For 16 bit Bus Master AEN - Address Enable

5. Associated Signals with ISA DMA SA [19:0] - System Address Bus La [ 23:7] - Latchable Address Bus SBHE# - System Bus High Enable

6. DMA Channel Assignments In ISA Channel 0 : Earlier was used for DRAM Refresh on 8bit ISA .Now its on 16 bit ISA used for 16 bit Bus Master Channel 1: For External Device Channel 2: Floppy And Hard drive Controller

7. DMA Channel Assignments In ISA Channel 3 : Hard disk controller Channel 5 : Hard disk controller Channel 6 & 7: External Device

8. Modes of DMA Transfers Single Transfer Mode Block Transfer Mode Demand Transfer Mode Cascaded Mode (used in 16 bit ISA Bus)

9. DMA Priority Logic Fixed Priority Rotating Priority

10. Addressing Capability of DMA Address Range of 16 MB 000000H-FFFFFFH This Can Achieved with 16bit Memory Address Register associated with DMA & 8bit external DMA Page Register

11. Addressing Capability of DMA Addressing for Slave DMA Addressing Master DMA Addressing The ISA Memory DMAC resides on X-bus & Addresses Bus on ISA Bus

12. When ISA MASTER requests for the Bus following Sequence Takes place Requesting device asserts DRQ line Master DMA 8237 asserts Hold request to the Microprocessor In response The Microprocessor asserts HLDA

13. Master DMAC asserts DAK line associated with respective DRQ line of Bus Master Now ISA Bus Master card should Asserts MASTER16# This causes AEN signal on ISA bus to be deasserted.

14. When ISA Bus Master has completed it uses of the bus it desasserts DRQ line And DMAC deasserts DAK and HOLD And this Deasserts HLDA line On Micro processor

15. Thank You Nishant H. Shah BE ETRX BATCH – B4 Roll No: 0412096