Direct Memory Access

1. UNIT 5
Direct Memory Access
DMA

2. Three Techniques for Input of a Block of Data

3. • Direct Memory Access (DMA) allows devices to transfer data
without subjecting the processor a heavy overhead.
• The processor would be unavailable for any other tasks involving
processor bus access.
• Processor can continue to work on any work which does not require
bus access.
• DMA transfers are essential for high performance embedded
systems where large chunks of data need to be transferred from
the input/output devices to or from the primary memory
About DMA Process

4. The two signals of 8085 Microprocessor work very effectively in 8237 DMA
Controller
1. HOLD
2. HLDA
HOLD
• Active High Input to the 8085.
• Used to inform 8085 that the external controller wants to do a direct memory
access.
• Remains high till the DMA process goes on.
• MPU completes current cycle and relinquishes the control of system buses to
DMA controller.
• MPU regains system buses after the HOLD goes low.
HLDA
• Active High output to confirm the grant of system buses by the 8085 to the
DMA Controller.

5. DMA Controller uses HOLD and HLDA by acting as a peripheral requesting for
the control of system buses.
MPU communicates with the controller using
1. Chip Select Lines
2. Buses
3. Control Signals
Once the DMA controller has gained buses, it acts as PROCESSOR for DATA
TRANSFER (Slave to MASTER MODE)
Controller needs following:
1. DATA BUS
2. ADDRESS BUS
3. CONTROL SIGNALS to disable role as peripheral and enable role As
Processor.

6. 8237 DMA CONTROLLER
• 40 PIN IC PACKAGE
• 4 INDEPENDENT CHANNELS
• Each channel capable of transferring 64K of data in one shot.
• Interfaces with :-
1. MPU
2. Peripherals
DMA Controller works as
1. I/O for the MPU - SLAVE MODE
2. Data Transfer Processor for the I/O Devices – MASTER MODE

7. DMA CHANNELS AND INTERFACING
1. 4 Independent Channels : CH0 to CH3
2. Every Channel has 2 , 16 Bit Registers
A. Register 1- MAR : Memory Address Register (16 Bit) : to hold the starting address of
the location from where the transfer begins
B. Register 2- Count Register : Holds the count of number of bytes to be transferred.
3. There are 8 such registers for the 4 Channels and can be accessed by MPU
4. Address lines A0 to A3 are used to address these registers.
5. There are some more registers which are used to write commands or read status.
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
CHIP SELECT 1 1 1 1

9. 8237 Pin Diagram

10. DMA Signals
1. DREQ0 to DREQ3: DMA Request: There are 4 independent asynchronous INPUT
signals from Peripherals for DMA request.
2. DACK0 to DACK3: DMA Acknowledge: O/P Lines to acknowledge the grant of
DMA.
DREQ and DACK are also called HANDSHAKING SIGNALS OF DMA
3. AEN and ADSTB : (o/p Signal) USED for Latch high order address byte to
generate the 16 bit address.
4. MEMR’ and MEMW’: O/P Signals used to read and write from memory during
the DMA process.
5. A3-A0 and A7-A4:
A3-A0: Bidirectional Control Lines, used as I/P to access control registers.
During DMA used as O/P lines to generate address portion A3-A0
A7-A4: used to generate an O/P address from A7-A4 during DMA

11. System Interface
DMA Controller has :
• 8 Data Lines
• 4 Control Signals: IOR’, IOW’, MEMR’,MEMW’
• 8 Address Lines
Needs 16 Address Lines to transfer a 16 bit address of memory location
Additional 8 address lines are required to generate the complete address??
DMA places lower address byte on Address bus
Higher Address byte on Data bus
Enables AEN and ADSTB to enable latching of Higher order address

13. DMA Execution
Slave Mode: DMA Treated as peripheral
1. MPU Selects the DMA Controller through Chip Select.
2. MP writes the control words in channels and command status registers by using IOW’ and
IOR’
Master Mode: 8237 keeps checking for a DMA request
1. When peripheral is ready , it sends DRQ
2. When DRQ is received and channel enabled, HRQ is made high which is connected to
HOLD
3. In next cycle MPU relinquished the control of System Buses
4. After receiving the HLDA signal, the DMA asserts AEN Signal High and cuts off the MPU
buses from MPU
5. When entire bus A0-A15 is available , DMA sends DACK to the peripheral.
6. DMA controller performs the data transfer till DACK remains high.
7. At the end of data transfer, EOP’ goes low to indicate the end of transfer to the peripheral.