This document discusses the operation and features of the 8237A DMA controller. It explains that DMA allows high-speed data transfer between memory and peripherals by bypassing the CPU. The 8237A has 4 independent channels that can each transfer 64KB of data. It interfaces with the CPU and peripherals using control signals like HOLD, HLDA, DREQ, and DACK. The 8237A has internal registers to store the starting address and transfer count for each channel. It generates 16-bit addresses using the lower address bits from its ports and the higher bits latched from the data bus.

1. A. S. M. Badrudduza, Asst. Prof., Dept. of ETE, RUET

2. DMA Operation

3. DMA Operation [Cntd.]
• Direct Memory Access (DMA) is an I/O technique commonly
used for high-speed data transfer; for example , data transfer
between memory and a floppy disk.
• In DMA, MPU releases the control of the buses to a device
called a DMA controller. The controller manages data
transfer between memory and a peripheral under its control,
thus bypassing the MPU.
• Two new signals HOLD and HLDA (Hold acknowledge) are
needed to complete DMA task.

4. HOLD
This is an active high input signal to MPU from another master requesting
the use of address and data busses.
The processor relinquishes the buses in the following machine cycle once
the MPU receives the HOLD request.
The busses are tri-stated and HLDA signal is sent out.
MPU regains the control of the buses after HOLD goes low.
HLDA
This is an active high output signal from MPU.
It indicates that the MPU is relinquishing the control of the buses.

5. DMA Controller Essentials
 A data bus,
 An address bus,
 Read/Write control signals, and
 Control signals to disable its role as a peripheral and
enable its role as a processor.

6. 8237A
DMA
Controller
with
Internal
Registers

7. Features of 8237A
8237 is a programmable Direct Memory Access controller (DMA)
housed in a 40-pin package.
It has four independent channels with each channel capable of
transferring 64K bytes.
It must interface with MPU and a peripheral device (floppy disk).
DMA plays two roles: i. it is an I/O device to MPU (slave mode) and ii.
it is a data transfer processor to peripheral device (master mode).
Many of its signals that are input in the I/O mode become outputs in
the processor mode.
It also needs additional signal lines to communicate with the
addresses of 64K data bytes which are generated externally by using
latches and buffers.

8. Description
8237 has four independent channels CH0-CH3. Two 16-bit registers
are internally associated with each channel: One is used to load the
starting address of the byte to be copied and the second is used to
load a count of the number of bytes to be copied.
These registers are determined by A3-A0 and the chip select line (CS).
Last 8 registers are used for writing commands and reading status.
The 8237 signals are divided into two groups: 1) signals on left (used
to communicate with MPU), and 2) signals on right (used to
communicate with peripheral).
Some of these signals are bidirectional and their functions are
determined by the DMA mode of operation (I/O or processor mode).

9. DMA Signals
DREQ0-DREQ3: Those are four independent, asynchronous input signals to the DMA
from peripherals. To obtain DMA service , a request is generated by activating the
DREQ line of the channel.
DACK0-DACK3: Those are output lines to inform the individual peripherals that DMA
is granted. DREQ and DACK are equivalent to handshake signals in I/O devices.
MEMR and MEMW: Those are output signals used during DMA cycle to write and
read from memory.
A3-A0 and A7-A4: A3-A0 lines are bidirectional. As input lines, they are used to
access control registers. During DMA cycle, those are output lines and are used to
generate low order address which are later combined with remaining lines A7-A4.
AEN and ADSTB: Address Enable and Address Strobe are used to latch a high-order
address byte to generate a 16-bit address.
HRQ and HLDA: After receiving the HRQ (Hold request), the MPU completes the bus
cycle in process and issues the HLDA (Hold Acknowledgement) signal.

10. DMA Interfacing with Microprocessor
DMA process includes 8 data lines, four control signals, 8 address lines. Additional
8 address lines are generated to access 64K bytes.
When a transfer begins, the DMA places the low-order byte on the address bus
and high-order byte on the data bus.
Then 8237 asserts AEN (Address Enable) and ADSTB (Address Strobe).
Theses two signals are used to latch the high-order byte from the data bus and
8237 places the 16-bit address on the system bus.
First latch (373 #1) is used to latch a high order address from the data bus and the
second latch (373 #2) is used to demultiplex the MPU bus and generate the low
order address bus.
The AEN signal is connected to OE signal of 373 #2 to disable the low order
address bus from the MPU when 373 #1 is enabled to latch the high order byte of
address.

11. Interfacing
8237A
DMA
Controller

12. Reference:
Ramesh Gaonkar, ‘Microprocessor, Architecture, Programming, and
Applications’, 5th Edition.